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Merge branch 'cunhuang/master' into 'master' (merge request !12) 

sync some ampere changes from upstream
This commit is contained in:
frankjpliu 2024-03-14 11:41:36 +00:00
parent dbc51490d1 3e14a8ae4f
commit da878504cf
25 changed files with 2296 additions and 77 deletions
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29
Documentation/admin-guide/perf/ampere_cspmu.rst Normal file
View File

@ -0,0 +1,29 @@
.. SPDX-License-Identifier: GPL-2.0
============================================
Ampere SoC Performance Monitoring Unit (PMU)
============================================
Ampere SoC PMU is a generic PMU IP that follows Arm CoreSight PMU architecture.
Therefore, the driver is implemented as a submodule of arm_cspmu driver. At the
first phase it's used for counting MCU events on AmpereOne.
MCU PMU events
--------------
The PMU driver supports setting filters for "rank", "bank", and "threshold".
Note, that the filters are per PMU instance rather than per event.
Example for perf tool use::
/ # perf list ampere
ampere_mcu_pmu_0/act_sent/ [Kernel PMU event]
<...>
ampere_mcu_pmu_1/rd_sent/ [Kernel PMU event]
<...>
/ # perf stat -a -e ampere_mcu_pmu_0/act_sent,bank=5,rank=3,threshold=2/,ampere_mcu_pmu_1/rd_sent/ \
sleep 1

1
Documentation/admin-guide/perf/index.rst
View File

@ -22,3 +22,4 @@ Performance monitor support
nvidia-pmu
meson-ddr-pmu
cxl
ampere_cspmu

37
arch/arm64/include/asm/kvm_mmu.h
View File

@ -224,16 +224,41 @@ static inline void __clean_dcache_guest_page(void *va, size_t size)
kvm_flush_dcache_to_poc(va, size);
}
static inline size_t __invalidate_icache_max_range(void)
{
u8 iminline;
u64 ctr;
asm volatile(ALTERNATIVE_CB("movz %0, #0\n"
"movk %0, #0, lsl #16\n"
"movk %0, #0, lsl #32\n"
"movk %0, #0, lsl #48\n",
ARM64_ALWAYS_SYSTEM,
kvm_compute_final_ctr_el0)
: "=r" (ctr));
iminline = SYS_FIELD_GET(CTR_EL0, IminLine, ctr) + 2;
return MAX_DVM_OPS << iminline;
}
static inline void __invalidate_icache_guest_page(void *va, size_t size)
{
if (icache_is_aliasing()) {
/* any kind of VIPT cache */
/*
* VPIPT I-cache maintenance must be done from EL2. See comment in the
* nVHE flavor of __kvm_tlb_flush_vmid_ipa().
*/
if (icache_is_vpipt() && read_sysreg(CurrentEL) != CurrentEL_EL2)
return;
/*
* Blow the whole I-cache if it is aliasing (i.e. VIPT) or the
* invalidation range exceeds our arbitrary limit on invadations by
* cache line.
*/
if (icache_is_aliasing() || size > __invalidate_icache_max_range())
icache_inval_all_pou();
} else if (read_sysreg(CurrentEL) != CurrentEL_EL1 ||
!icache_is_vpipt()) {
/* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */
else
icache_inval_pou((unsigned long)va, (unsigned long)va + size);
}
}
void kvm_set_way_flush(struct kvm_vcpu *vcpu);

8
arch/arm64/include/asm/tlbflush.h
View File

@ -333,7 +333,7 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
* This is meant to avoid soft lock-ups on large TLB flushing ranges and not
* necessarily a performance improvement.
*/
#define MAX_TLBI_OPS PTRS_PER_PTE
#define MAX_DVM_OPS PTRS_PER_PTE
/*
* __flush_tlb_range_op - Perform TLBI operation upon a range
@ -413,12 +413,12 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
/*
* When not uses TLB range ops, we can handle up to
* (MAX_TLBI_OPS - 1) pages;
* (MAX_DVM_OPS - 1) pages;
* When uses TLB range ops, we can handle up to
* (MAX_TLBI_RANGE_PAGES - 1) pages.
*/
if ((!system_supports_tlb_range() &&
(end - start) >= (MAX_TLBI_OPS * stride)) ||
(end - start) >= (MAX_DVM_OPS * stride)) ||
pages >= MAX_TLBI_RANGE_PAGES) {
flush_tlb_mm(vma->vm_mm);
return;
@ -451,7 +451,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
{
unsigned long addr;
if ((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) {
if ((end - start) > (MAX_DVM_OPS * PAGE_SIZE)) {
flush_tlb_all();
return;
}

2
arch/arm64/kvm/hyp/pgtable.c
View File

@ -1314,7 +1314,7 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr,
ret = stage2_update_leaf_attrs(pgt, addr, 1, set, clr, NULL, &level,
KVM_PGTABLE_WALK_HANDLE_FAULT |
KVM_PGTABLE_WALK_SHARED);
if (!ret)
if (!ret || ret == -EAGAIN)
kvm_call_hyp(__kvm_tlb_flush_vmid_ipa_nsh, pgt->mmu, addr, level);
return ret;
}

19
drivers/perf/arm_cspmu/Kconfig
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
config ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
tristate "ARM Coresight Architecture PMU"
@ -10,3 +10,20 @@ config ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
based on ARM CoreSight PMU architecture. Note that this PMU
architecture does not have relationship with the ARM CoreSight
Self-Hosted Tracing.
config NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU
tristate "NVIDIA Coresight Architecture PMU"
depends on ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
help
Provides NVIDIA specific attributes for performance monitoring unit
(PMU) devices based on ARM CoreSight PMU architecture.
config AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU
tristate "Ampere Coresight Architecture PMU"
depends on ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
help
Provides Ampere specific attributes for performance monitoring unit
(PMU) devices based on ARM CoreSight PMU architecture.
In the first phase, the driver enables support on MCU PMU used in
AmpereOne SoC family.

8
drivers/perf/arm_cspmu/Makefile
View File

@ -1,6 +1,10 @@
# Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += arm_cspmu_module.o
arm_cspmu_module-y := arm_cspmu.o nvidia_cspmu.o
arm_cspmu_module-y := arm_cspmu.o
obj-$(CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += nvidia_cspmu.o
obj-$(CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += ampere_cspmu.o

272
drivers/perf/arm_cspmu/ampere_cspmu.c Normal file
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@ -0,0 +1,272 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Ampere SoC PMU (Performance Monitor Unit)
*
* Copyright (c) 2023, Ampere Computing LLC
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/topology.h>
#include "arm_cspmu.h"
#define PMAUXR0 0xD80
#define PMAUXR1 0xD84
#define PMAUXR2 0xD88
#define PMAUXR3 0xD8C
#define to_ampere_cspmu_ctx(cspmu) ((struct ampere_cspmu_ctx *)(cspmu->impl.ctx))
struct ampere_cspmu_ctx {
const char *name;
struct attribute **event_attr;
struct attribute **format_attr;
};
static DEFINE_IDA(mcu_pmu_ida);
#define SOC_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) \
static inline u32 get_##_name(const struct perf_event *event) \
{ \
return FIELD_GET(GENMASK_ULL(_end, _start), \
event->attr._config); \
} \
SOC_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 8);
SOC_PMU_EVENT_ATTR_EXTRACTOR(threshold, config1, 0, 7);
SOC_PMU_EVENT_ATTR_EXTRACTOR(rank, config1, 8, 23);
SOC_PMU_EVENT_ATTR_EXTRACTOR(bank, config1, 24, 55);
static struct attribute *ampereone_mcu_pmu_event_attrs[] = {
ARM_CSPMU_EVENT_ATTR(cycle_count, 0x00),
ARM_CSPMU_EVENT_ATTR(act_sent, 0x01),
ARM_CSPMU_EVENT_ATTR(pre_sent, 0x02),
ARM_CSPMU_EVENT_ATTR(rd_sent, 0x03),
ARM_CSPMU_EVENT_ATTR(rda_sent, 0x04),
ARM_CSPMU_EVENT_ATTR(wr_sent, 0x05),
ARM_CSPMU_EVENT_ATTR(wra_sent, 0x06),
ARM_CSPMU_EVENT_ATTR(pd_entry_vld, 0x07),
ARM_CSPMU_EVENT_ATTR(sref_entry_vld, 0x08),
ARM_CSPMU_EVENT_ATTR(prea_sent, 0x09),
ARM_CSPMU_EVENT_ATTR(pre_sb_sent, 0x0a),
ARM_CSPMU_EVENT_ATTR(ref_sent, 0x0b),
ARM_CSPMU_EVENT_ATTR(rfm_sent, 0x0c),
ARM_CSPMU_EVENT_ATTR(ref_sb_sent, 0x0d),
ARM_CSPMU_EVENT_ATTR(rfm_sb_sent, 0x0e),
ARM_CSPMU_EVENT_ATTR(rd_rda_sent, 0x0f),
ARM_CSPMU_EVENT_ATTR(wr_wra_sent, 0x10),
ARM_CSPMU_EVENT_ATTR(raw_hazard, 0x11),
ARM_CSPMU_EVENT_ATTR(war_hazard, 0x12),
ARM_CSPMU_EVENT_ATTR(waw_hazard, 0x13),
ARM_CSPMU_EVENT_ATTR(rar_hazard, 0x14),
ARM_CSPMU_EVENT_ATTR(raw_war_waw_hazard, 0x15),
ARM_CSPMU_EVENT_ATTR(hprd_lprd_wr_req_vld, 0x16),
ARM_CSPMU_EVENT_ATTR(lprd_req_vld, 0x17),
ARM_CSPMU_EVENT_ATTR(hprd_req_vld, 0x18),
ARM_CSPMU_EVENT_ATTR(hprd_lprd_req_vld, 0x19),
ARM_CSPMU_EVENT_ATTR(prefetch_tgt, 0x1a),
ARM_CSPMU_EVENT_ATTR(wr_req_vld, 0x1b),
ARM_CSPMU_EVENT_ATTR(partial_wr_req_vld, 0x1c),
ARM_CSPMU_EVENT_ATTR(rd_retry, 0x1d),
ARM_CSPMU_EVENT_ATTR(wr_retry, 0x1e),
ARM_CSPMU_EVENT_ATTR(retry_gnt, 0x1f),
ARM_CSPMU_EVENT_ATTR(rank_change, 0x20),
ARM_CSPMU_EVENT_ATTR(dir_change, 0x21),
ARM_CSPMU_EVENT_ATTR(rank_dir_change, 0x22),
ARM_CSPMU_EVENT_ATTR(rank_active, 0x23),
ARM_CSPMU_EVENT_ATTR(rank_idle, 0x24),
ARM_CSPMU_EVENT_ATTR(rank_pd, 0x25),
ARM_CSPMU_EVENT_ATTR(rank_sref, 0x26),
ARM_CSPMU_EVENT_ATTR(queue_fill_gt_thresh, 0x27),
ARM_CSPMU_EVENT_ATTR(queue_rds_gt_thresh, 0x28),
ARM_CSPMU_EVENT_ATTR(queue_wrs_gt_thresh, 0x29),
ARM_CSPMU_EVENT_ATTR(phy_updt_complt, 0x2a),
ARM_CSPMU_EVENT_ATTR(tz_fail, 0x2b),
ARM_CSPMU_EVENT_ATTR(dram_errc, 0x2c),
ARM_CSPMU_EVENT_ATTR(dram_errd, 0x2d),
ARM_CSPMU_EVENT_ATTR(read_data_return, 0x32),
ARM_CSPMU_EVENT_ATTR(chi_wr_data_delta, 0x33),
ARM_CSPMU_EVENT_ATTR(zq_start, 0x34),
ARM_CSPMU_EVENT_ATTR(zq_latch, 0x35),
ARM_CSPMU_EVENT_ATTR(wr_fifo_full, 0x36),
ARM_CSPMU_EVENT_ATTR(info_fifo_full, 0x37),
ARM_CSPMU_EVENT_ATTR(cmd_fifo_full, 0x38),
ARM_CSPMU_EVENT_ATTR(dfi_nop, 0x39),
ARM_CSPMU_EVENT_ATTR(dfi_cmd, 0x3a),
ARM_CSPMU_EVENT_ATTR(rd_run_len, 0x3b),
ARM_CSPMU_EVENT_ATTR(wr_run_len, 0x3c),
ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT),
NULL,
};
static struct attribute *ampereone_mcu_format_attrs[] = {
ARM_CSPMU_FORMAT_EVENT_ATTR,
ARM_CSPMU_FORMAT_ATTR(threshold, "config1:0-7"),
ARM_CSPMU_FORMAT_ATTR(rank, "config1:8-23"),
ARM_CSPMU_FORMAT_ATTR(bank, "config1:24-55"),
NULL,
};
static struct attribute **
ampere_cspmu_get_event_attrs(const struct arm_cspmu *cspmu)
{
const struct ampere_cspmu_ctx *ctx = to_ampere_cspmu_ctx(cspmu);
return ctx->event_attr;
}
static struct attribute **
ampere_cspmu_get_format_attrs(const struct arm_cspmu *cspmu)
{
const struct ampere_cspmu_ctx *ctx = to_ampere_cspmu_ctx(cspmu);
return ctx->format_attr;
}
static const char *
ampere_cspmu_get_name(const struct arm_cspmu *cspmu)
{
const struct ampere_cspmu_ctx *ctx = to_ampere_cspmu_ctx(cspmu);
return ctx->name;
}
static u32 ampere_cspmu_event_filter(const struct perf_event *event)
{
/*
* PMEVFILTR or PMCCFILTR aren't used in Ampere SoC PMU but are marked
* as RES0. Make sure, PMCCFILTR is written zero.
*/
return 0;
}
static void ampere_cspmu_set_ev_filter(struct arm_cspmu *cspmu,
struct hw_perf_event *hwc,
u32 filter)
{
struct perf_event *event;
unsigned int idx;
u32 threshold, rank, bank;
/*
* At this point, all the events have the same filter settings.
* Therefore, take the first event and use its configuration.
*/
idx = find_first_bit(cspmu->hw_events.used_ctrs,
cspmu->cycle_counter_logical_idx);
event = cspmu->hw_events.events[idx];
threshold = get_threshold(event);
rank = get_rank(event);
bank = get_bank(event);
writel(threshold, cspmu->base0 + PMAUXR0);
writel(rank, cspmu->base0 + PMAUXR1);
writel(bank, cspmu->base0 + PMAUXR2);
}
static int ampere_cspmu_validate_configs(struct perf_event *event,
struct perf_event *event2)
{
if (get_threshold(event) != get_threshold(event2) ||
get_rank(event) != get_rank(event2) ||
get_bank(event) != get_bank(event2))
return -EINVAL;
return 0;
}
static int ampere_cspmu_validate_event(struct arm_cspmu *cspmu,
struct perf_event *new)
{
struct perf_event *curr, *leader = new->group_leader;
unsigned int idx;
int ret;
ret = ampere_cspmu_validate_configs(new, leader);
if (ret)
return ret;
/* We compare the global filter settings to the existing events */
idx = find_first_bit(cspmu->hw_events.used_ctrs,
cspmu->cycle_counter_logical_idx);
/* This is the first event, thus any configuration is fine */
if (idx == cspmu->cycle_counter_logical_idx)
return 0;
curr = cspmu->hw_events.events[idx];
return ampere_cspmu_validate_configs(curr, new);
}
static char *ampere_cspmu_format_name(const struct arm_cspmu *cspmu,
const char *name_pattern)
{
struct device *dev = cspmu->dev;
int id;
id = ida_alloc(&mcu_pmu_ida, GFP_KERNEL);
if (id < 0)
return ERR_PTR(id);
return devm_kasprintf(dev, GFP_KERNEL, name_pattern, id);
}
static int ampere_cspmu_init_ops(struct arm_cspmu *cspmu)
{
struct device *dev = cspmu->dev;
struct ampere_cspmu_ctx *ctx;
struct arm_cspmu_impl_ops *impl_ops = &cspmu->impl.ops;
ctx = devm_kzalloc(dev, sizeof(struct ampere_cspmu_ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ctx->event_attr = ampereone_mcu_pmu_event_attrs;
ctx->format_attr = ampereone_mcu_format_attrs;
ctx->name = ampere_cspmu_format_name(cspmu, "ampere_mcu_pmu_%d");
if (IS_ERR_OR_NULL(ctx->name))
return ctx->name ? PTR_ERR(ctx->name) : -ENOMEM;
cspmu->impl.ctx = ctx;
impl_ops->event_filter = ampere_cspmu_event_filter;
impl_ops->set_ev_filter = ampere_cspmu_set_ev_filter;
impl_ops->validate_event = ampere_cspmu_validate_event;
impl_ops->get_name = ampere_cspmu_get_name;
impl_ops->get_event_attrs = ampere_cspmu_get_event_attrs;
impl_ops->get_format_attrs = ampere_cspmu_get_format_attrs;
return 0;
}
/* Match all Ampere Coresight PMU devices */
static const struct arm_cspmu_impl_match ampere_cspmu_param = {
.pmiidr_val = ARM_CSPMU_IMPL_ID_AMPERE,
.module = THIS_MODULE,
.impl_init_ops = ampere_cspmu_init_ops
};
static int __init ampere_cspmu_init(void)
{
int ret;
ret = arm_cspmu_impl_register(&ampere_cspmu_param);
if (ret)
pr_err("ampere_cspmu backend registration error: %d\n", ret);
return ret;
}
static void __exit ampere_cspmu_exit(void)
{
arm_cspmu_impl_unregister(&ampere_cspmu_param);
}
module_init(ampere_cspmu_init);
module_exit(ampere_cspmu_exit);
MODULE_LICENSE("GPL");

201
drivers/perf/arm_cspmu/arm_cspmu.c
View File

@ -16,7 +16,7 @@
* The user should refer to the vendor technical documentation to get details
* about the supported events.
*
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
*/
@ -26,11 +26,11 @@
#include <linux/interrupt.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#include "arm_cspmu.h"
#include "nvidia_cspmu.h"
#define PMUNAME "arm_cspmu"
#define DRVNAME "arm-cs-arch-pmu"
@ -112,11 +112,13 @@
*/
#define HILOHI_MAX_POLL 1000
/* JEDEC-assigned JEP106 identification code */
#define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B
static unsigned long arm_cspmu_cpuhp_state;
static DEFINE_MUTEX(arm_cspmu_lock);
static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu,
struct hw_perf_event *hwc, u32 filter);
static struct acpi_apmt_node *arm_cspmu_apmt_node(struct device *dev)
{
return *(struct acpi_apmt_node **)dev_get_platdata(dev);
@ -373,27 +375,45 @@ static struct attribute_group arm_cspmu_cpumask_attr_group = {
.attrs = arm_cspmu_cpumask_attrs,
};
struct impl_match {
u32 pmiidr;
u32 mask;
int (*impl_init_ops)(struct arm_cspmu *cspmu);
static struct arm_cspmu_impl_match impl_match[] = {
{
.module_name = "nvidia_cspmu",
.pmiidr_val = ARM_CSPMU_IMPL_ID_NVIDIA,
.pmiidr_mask = ARM_CSPMU_PMIIDR_IMPLEMENTER,
.module = NULL,
.impl_init_ops = NULL,
},
{
.module_name = "ampere_cspmu",
.pmiidr_val = ARM_CSPMU_IMPL_ID_AMPERE,
.pmiidr_mask = ARM_CSPMU_PMIIDR_IMPLEMENTER,
.module = NULL,
.impl_init_ops = NULL,
},
{0}
};
static const struct impl_match impl_match[] = {
{
.pmiidr = ARM_CSPMU_IMPL_ID_NVIDIA,
.mask = ARM_CSPMU_PMIIDR_IMPLEMENTER,
.impl_init_ops = nv_cspmu_init_ops
},
{}
};
static struct arm_cspmu_impl_match *arm_cspmu_impl_match_get(u32 pmiidr)
{
struct arm_cspmu_impl_match *match = impl_match;
for (; match->pmiidr_val; match++) {
u32 mask = match->pmiidr_mask;
if ((match->pmiidr_val & mask) == (pmiidr & mask))
return match;
}
return NULL;
}
static int arm_cspmu_init_impl_ops(struct arm_cspmu *cspmu)
{
int ret;
int ret = 0;
struct arm_cspmu_impl_ops *impl_ops = &cspmu->impl.ops;
struct acpi_apmt_node *apmt_node = arm_cspmu_apmt_node(cspmu->dev);
const struct impl_match *match = impl_match;
struct arm_cspmu_impl_match *match;
/*
* Get PMU implementer and product id from APMT node.
@ -405,17 +425,36 @@ static int arm_cspmu_init_impl_ops(struct arm_cspmu *cspmu)
readl(cspmu->base0 + PMIIDR);
/* Find implementer specific attribute ops. */
for (; match->pmiidr; match++) {
const u32 mask = match->mask;
match = arm_cspmu_impl_match_get(cspmu->impl.pmiidr);
if ((match->pmiidr & mask) == (cspmu->impl.pmiidr & mask)) {
ret = match->impl_init_ops(cspmu);
if (ret)
return ret;
/* Load implementer module and initialize the callbacks. */
if (match) {
mutex_lock(&arm_cspmu_lock);
break;
if (match->impl_init_ops) {
/* Prevent unload until PMU registration is done. */
if (try_module_get(match->module)) {
cspmu->impl.module = match->module;
cspmu->impl.match = match;
ret = match->impl_init_ops(cspmu);
if (ret)
module_put(match->module);
} else {
WARN(1, "arm_cspmu failed to get module: %s\n",
match->module_name);
ret = -EINVAL;
}
} else {
request_module_nowait(match->module_name);
ret = -EPROBE_DEFER;
}
}
mutex_unlock(&arm_cspmu_lock);
if (ret)
return ret;
} else
cspmu->impl.module = THIS_MODULE;
/* Use default callbacks if implementer doesn't provide one. */
CHECK_DEFAULT_IMPL_OPS(impl_ops, get_event_attrs);
@ -426,6 +465,7 @@ static int arm_cspmu_init_impl_ops(struct arm_cspmu *cspmu)
CHECK_DEFAULT_IMPL_OPS(impl_ops, event_type);
CHECK_DEFAULT_IMPL_OPS(impl_ops, event_filter);
CHECK_DEFAULT_IMPL_OPS(impl_ops, event_attr_is_visible);
CHECK_DEFAULT_IMPL_OPS(impl_ops, set_ev_filter);
return 0;
}
@ -478,11 +518,6 @@ arm_cspmu_alloc_attr_group(struct arm_cspmu *cspmu)
struct attribute_group **attr_groups = NULL;
struct device *dev = cspmu->dev;
const struct arm_cspmu_impl_ops *impl_ops = &cspmu->impl.ops;
int ret;
ret = arm_cspmu_init_impl_ops(cspmu);
if (ret)
return NULL;
cspmu->identifier = impl_ops->get_identifier(cspmu);
cspmu->name = impl_ops->get_name(cspmu);
@ -549,7 +584,7 @@ static void arm_cspmu_disable(struct pmu *pmu)
static int arm_cspmu_get_event_idx(struct arm_cspmu_hw_events *hw_events,
struct perf_event *event)
{
int idx;
int idx, ret;
struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);
if (supports_cycle_counter(cspmu)) {
@ -583,6 +618,12 @@ static int arm_cspmu_get_event_idx(struct arm_cspmu_hw_events *hw_events,
if (idx >= cspmu->num_logical_ctrs)
return -EAGAIN;
if (cspmu->impl.ops.validate_event) {
ret = cspmu->impl.ops.validate_event(cspmu, event);
if (ret)
return ret;
}
set_bit(idx, hw_events->used_ctrs);
return idx;
@ -699,7 +740,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val)
if (use_64b_counter_reg(cspmu)) {
offset = counter_offset(sizeof(u64), event->hw.idx);
writeq(val, cspmu->base1 + offset);
if (cspmu->has_atomic_dword)
writeq(val, cspmu->base1 + offset);
else
lo_hi_writeq(val, cspmu->base1 + offset);
} else {
offset = counter_offset(sizeof(u32), event->hw.idx);
@ -792,9 +836,9 @@ static inline void arm_cspmu_set_event(struct arm_cspmu *cspmu,
writel(hwc->config, cspmu->base0 + offset);
}
static inline void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu,
struct hw_perf_event *hwc,
u32 filter)
static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu,
struct hw_perf_event *hwc,
u32 filter)
{
u32 offset = PMEVFILTR + (4 * hwc->idx);
@ -826,7 +870,7 @@ static void arm_cspmu_start(struct perf_event *event, int pmu_flags)
arm_cspmu_set_cc_filter(cspmu, filter);
} else {
arm_cspmu_set_event(cspmu, hwc);
arm_cspmu_set_ev_filter(cspmu, hwc, filter);
cspmu->impl.ops.set_ev_filter(cspmu, hwc, filter);
}
hwc->state = 0;
@ -1152,7 +1196,7 @@ static int arm_cspmu_register_pmu(struct arm_cspmu *cspmu)
cspmu->pmu = (struct pmu){
.task_ctx_nr = perf_invalid_context,
.module = THIS_MODULE,
.module = cspmu->impl.module,
.pmu_enable = arm_cspmu_enable,
.pmu_disable = arm_cspmu_disable,
.event_init = arm_cspmu_event_init,
@ -1199,11 +1243,17 @@ static int arm_cspmu_device_probe(struct platform_device *pdev)
if (ret)
return ret;
ret = arm_cspmu_register_pmu(cspmu);
ret = arm_cspmu_init_impl_ops(cspmu);
if (ret)
return ret;
return 0;
ret = arm_cspmu_register_pmu(cspmu);
/* Matches arm_cspmu_init_impl_ops() above. */
if (cspmu->impl.module != THIS_MODULE)
module_put(cspmu->impl.module);
return ret;
}
static int arm_cspmu_device_remove(struct platform_device *pdev)
@ -1303,6 +1353,75 @@ static void __exit arm_cspmu_exit(void)
cpuhp_remove_multi_state(arm_cspmu_cpuhp_state);
}
int arm_cspmu_impl_register(const struct arm_cspmu_impl_match *impl_match)
{
struct arm_cspmu_impl_match *match;
int ret = 0;
match = arm_cspmu_impl_match_get(impl_match->pmiidr_val);
if (match) {
mutex_lock(&arm_cspmu_lock);
if (!match->impl_init_ops) {
match->module = impl_match->module;
match->impl_init_ops = impl_match->impl_init_ops;
} else {
/* Broken match table may contain non-unique entries */
WARN(1, "arm_cspmu backend already registered for module: %s, pmiidr: 0x%x, mask: 0x%x\n",
match->module_name,
match->pmiidr_val,
match->pmiidr_mask);
ret = -EINVAL;
}
mutex_unlock(&arm_cspmu_lock);
if (!ret)
ret = driver_attach(&arm_cspmu_driver.driver);
} else {
pr_err("arm_cspmu reg failed, unable to find a match for pmiidr: 0x%x\n",
impl_match->pmiidr_val);
ret = -EINVAL;
}
return ret;
}
EXPORT_SYMBOL_GPL(arm_cspmu_impl_register);
static int arm_cspmu_match_device(struct device *dev, const void *match)
{
struct arm_cspmu *cspmu = platform_get_drvdata(to_platform_device(dev));
return (cspmu && cspmu->impl.match == match) ? 1 : 0;
}
void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_match)
{
struct device *dev;
struct arm_cspmu_impl_match *match;
match = arm_cspmu_impl_match_get(impl_match->pmiidr_val);
if (WARN_ON(!match))
return;
/* Unbind the driver from all matching backend devices. */
while ((dev = driver_find_device(&arm_cspmu_driver.driver, NULL,
match, arm_cspmu_match_device)))
device_release_driver(dev);
mutex_lock(&arm_cspmu_lock);
match->module = NULL;
match->impl_init_ops = NULL;
mutex_unlock(&arm_cspmu_lock);
}
EXPORT_SYMBOL_GPL(arm_cspmu_impl_unregister);
module_init(arm_cspmu_init);
module_exit(arm_cspmu_exit);

32
drivers/perf/arm_cspmu/arm_cspmu.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0
*
* ARM CoreSight Architecture PMU driver.
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
*/
@ -69,6 +69,10 @@
#define ARM_CSPMU_PMIIDR_IMPLEMENTER GENMASK(11, 0)
#define ARM_CSPMU_PMIIDR_PRODUCTID GENMASK(31, 20)
/* JEDEC-assigned JEP106 identification code */
#define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B
#define ARM_CSPMU_IMPL_ID_AMPERE 0xA16
struct arm_cspmu;
/* This tracks the events assigned to each counter in the PMU. */
@ -101,14 +105,34 @@ struct arm_cspmu_impl_ops {
u32 (*event_type)(const struct perf_event *event);
/* Decode filter value from configs */
u32 (*event_filter)(const struct perf_event *event);
/* Set event filter */
void (*set_ev_filter)(struct arm_cspmu *cspmu,
struct hw_perf_event *hwc, u32 filter);
/* Implementation specific event validation */
int (*validate_event)(struct arm_cspmu *cspmu,
struct perf_event *event);
/* Hide/show unsupported events */
umode_t (*event_attr_is_visible)(struct kobject *kobj,
struct attribute *attr, int unused);
};
/* Vendor/implementer registration parameter. */
struct arm_cspmu_impl_match {
/* Backend module. */
struct module *module;
const char *module_name;
/* PMIIDR value/mask. */
u32 pmiidr_val;
u32 pmiidr_mask;
/* Callback to vendor backend to init arm_cspmu_impl::ops. */
int (*impl_init_ops)(struct arm_cspmu *cspmu);
};
/* Vendor/implementer descriptor. */
struct arm_cspmu_impl {
u32 pmiidr;
struct module *module;
struct arm_cspmu_impl_match *match;
struct arm_cspmu_impl_ops ops;
void *ctx;
};
@ -147,4 +171,10 @@ ssize_t arm_cspmu_sysfs_format_show(struct device *dev,
struct device_attribute *attr,
char *buf);
/* Register vendor backend. */
int arm_cspmu_impl_register(const struct arm_cspmu_impl_match *impl_match);
/* Unregister vendor backend. */
void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_match);
#endif /* __ARM_CSPMU_H__ */

34
drivers/perf/arm_cspmu/nvidia_cspmu.c
View File

@ -1,14 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
*/
/* Support for NVIDIA specific attributes. */
#include <linux/module.h>
#include <linux/topology.h>
#include "nvidia_cspmu.h"
#include "arm_cspmu.h"
#define NV_PCIE_PORT_COUNT 10ULL
#define NV_PCIE_FILTER_ID_MASK GENMASK_ULL(NV_PCIE_PORT_COUNT - 1, 0)
@ -351,7 +352,7 @@ static char *nv_cspmu_format_name(const struct arm_cspmu *cspmu,
return name;
}
int nv_cspmu_init_ops(struct arm_cspmu *cspmu)
static int nv_cspmu_init_ops(struct arm_cspmu *cspmu)
{
u32 prodid;
struct nv_cspmu_ctx *ctx;
@ -395,6 +396,31 @@ int nv_cspmu_init_ops(struct arm_cspmu *cspmu)
return 0;
}
EXPORT_SYMBOL_GPL(nv_cspmu_init_ops);
/* Match all NVIDIA Coresight PMU devices */
static const struct arm_cspmu_impl_match nv_cspmu_param = {
.pmiidr_val = ARM_CSPMU_IMPL_ID_NVIDIA,
.module = THIS_MODULE,
.impl_init_ops = nv_cspmu_init_ops
};
static int __init nvidia_cspmu_init(void)
{
int ret;
ret = arm_cspmu_impl_register(&nv_cspmu_param);
if (ret)
pr_err("nvidia_cspmu backend registration error: %d\n", ret);
return ret;
}
static void __exit nvidia_cspmu_exit(void)
{
arm_cspmu_impl_unregister(&nv_cspmu_param);
}
module_init(nvidia_cspmu_init);
module_exit(nvidia_cspmu_exit);
MODULE_LICENSE("GPL v2");

17
drivers/perf/arm_cspmu/nvidia_cspmu.h
View File

@ -1,17 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
*/
/* Support for NVIDIA specific attributes. */
#ifndef __NVIDIA_CSPMU_H__
#define __NVIDIA_CSPMU_H__
#include "arm_cspmu.h"
/* Allocate NVIDIA descriptor. */
int nv_cspmu_init_ops(struct arm_cspmu *cspmu);
#endif /* __NVIDIA_CSPMU_H__ */

125
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/branch.json Normal file
View File

@ -0,0 +1,125 @@
[
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "BR_MIS_PRED"
},
{
"ArchStdEvent": "BR_PRED"
},
{
"PublicDescription": "Instruction architecturally executed, branch not taken",
"EventCode": "0x8107",
"EventName": "BR_SKIP_RETIRED",
"BriefDescription": "Instruction architecturally executed, branch not taken"
},
{
"PublicDescription": "Instruction architecturally executed, immediate branch taken",
"EventCode": "0x8108",
"EventName": "BR_IMMED_TAKEN_RETIRED",
"BriefDescription": "Instruction architecturally executed, immediate branch taken"
},
{
"PublicDescription": "Instruction architecturally executed, indirect branch excluding return retired",
"EventCode": "0x810c",
"EventName": "BR_INDNR_TAKEN_RETIRED",
"BriefDescription": "Instruction architecturally executed, indirect branch excluding return retired"
},
{
"PublicDescription": "Instruction architecturally executed, predicted immediate branch",
"EventCode": "0x8110",
"EventName": "BR_IMMED_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted immediate branch"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted immediate branch",
"EventCode": "0x8111",
"EventName": "BR_IMMED_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted immediate branch"
},
{
"PublicDescription": "Instruction architecturally executed, predicted indirect branch",
"EventCode": "0x8112",
"EventName": "BR_IND_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted indirect branch"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch",
"EventCode": "0x8113",
"EventName": "BR_IND_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch"
},
{
"PublicDescription": "Instruction architecturally executed, predicted procedure return",
"EventCode": "0x8114",
"EventName": "BR_RETURN_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted procedure return"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted procedure return",
"EventCode": "0x8115",
"EventName": "BR_RETURN_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted procedure return"
},
{
"PublicDescription": "Instruction architecturally executed, predicted indirect branch excluding return",
"EventCode": "0x8116",
"EventName": "BR_INDNR_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted indirect branch excluding return"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return",
"EventCode": "0x8117",
"EventName": "BR_INDNR_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch excluding return"
},
{
"PublicDescription": "Instruction architecturally executed, predicted branch, taken",
"EventCode": "0x8118",
"EventName": "BR_TAKEN_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted branch, taken"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted branch, taken",
"EventCode": "0x8119",
"EventName": "BR_TAKEN_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted branch, taken"
},
{
"PublicDescription": "Instruction architecturally executed, predicted branch, not taken",
"EventCode": "0x811a",
"EventName": "BR_SKIP_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted branch, not taken"
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted branch, not taken",
"EventCode": "0x811b",
"EventName": "BR_SKIP_MIS_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, mispredicted branch, not taken"
},
{
"PublicDescription": "Instruction architecturally executed, predicted branch",
"EventCode": "0x811c",
"EventName": "BR_PRED_RETIRED",
"BriefDescription": "Instruction architecturally executed, predicted branch"
},
{
"PublicDescription": "Instruction architecturally executed, indirect branch",
"EventCode": "0x811d",
"EventName": "BR_IND_RETIRED",
"BriefDescription": "Instruction architecturally executed, indirect branch"
},
{
"PublicDescription": "Branch Record captured.",
"EventCode": "0x811f",
"EventName": "BRB_FILTRATE",
"BriefDescription": "Branch Record captured."
}
]

20
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/bus.json Normal file
View File

@ -0,0 +1,20 @@
[
{
"ArchStdEvent": "CPU_CYCLES"
},
{
"ArchStdEvent": "BUS_CYCLES"
},
{
"ArchStdEvent": "BUS_ACCESS_RD"
},
{
"ArchStdEvent": "BUS_ACCESS_WR"
},
{
"ArchStdEvent": "BUS_ACCESS"
},
{
"ArchStdEvent": "CNT_CYCLES"
}
]

206
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json Normal file
View File

@ -0,0 +1,206 @@
[
{
"ArchStdEvent": "L1D_CACHE_RD"
},
{
"ArchStdEvent": "L1D_CACHE_WR"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L1D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_RD"
},
{
"ArchStdEvent": "L2D_CACHE_WR"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"ArchStdEvent": "L1I_CACHE_REFILL"
},
{
"ArchStdEvent": "L1I_TLB_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL"
},
{
"ArchStdEvent": "L1D_CACHE"
},
{
"ArchStdEvent": "L1D_TLB_REFILL"
},
{
"ArchStdEvent": "L1I_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE"
},
{
"ArchStdEvent": "L2D_CACHE_REFILL"
},
{
"ArchStdEvent": "L2D_CACHE_WB"
},
{
"ArchStdEvent": "L1D_TLB"
},
{
"ArchStdEvent": "L1I_TLB"
},
{
"ArchStdEvent": "L2D_TLB_REFILL"
},
{
"ArchStdEvent": "L2I_TLB_REFILL"
},
{
"ArchStdEvent": "L2D_TLB"
},
{
"ArchStdEvent": "L2I_TLB"
},
{
"ArchStdEvent": "DTLB_WALK"
},
{
"ArchStdEvent": "ITLB_WALK"
},
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
"ArchStdEvent": "L1D_CACHE_LMISS_RD"
},
{
"ArchStdEvent": "L1I_CACHE_LMISS"
},
{
"ArchStdEvent": "L2D_CACHE_LMISS_RD"
},
{
"PublicDescription": "Level 1 data or unified cache demand access",
"EventCode": "0x8140",
"EventName": "L1D_CACHE_RW",
"BriefDescription": "Level 1 data or unified cache demand access"
},
{
"PublicDescription": "Level 1 data or unified cache preload or prefetch",
"EventCode": "0x8142",
"EventName": "L1D_CACHE_PRFM",
"BriefDescription": "Level 1 data or unified cache preload or prefetch"
},
{
"PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
"EventCode": "0x8146",
"EventName": "L1D_CACHE_REFILL_PRFM",
"BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
},
{
"ArchStdEvent": "L1D_TLB_RD"
},
{
"ArchStdEvent": "L1D_TLB_WR"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_RD"
},
{
"ArchStdEvent": "L2D_TLB_REFILL_WR"
},
{
"ArchStdEvent": "L2D_TLB_RD"
},
{
"ArchStdEvent": "L2D_TLB_WR"
},
{
"PublicDescription": "L1D TLB miss",
"EventCode": "0xD600",
"EventName": "L1D_TLB_MISS",
"BriefDescription": "L1D TLB miss"
},
{
"PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
"EventCode": "0xd606",
"EventName": "L1_PREFETCH_LD_GEN",
"BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
},
{
"PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",
"EventCode": "0xd607",
"EventName": "L1_PREFETCH_LD_FILL",
"BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"
},
{
"PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",
"EventCode": "0xd608",
"EventName": "L1_PREFETCH_L2_REQ",
"BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"
},
{
"PublicDescription": "L1 prefetcher, distance was reset",
"EventCode": "0xd609",
"EventName": "L1_PREFETCH_DIST_RST",
"BriefDescription": "L1 prefetcher, distance was reset"
},
{
"PublicDescription": "L1 prefetcher, distance was increased",
"EventCode": "0xd60a",
"EventName": "L1_PREFETCH_DIST_INC",
"BriefDescription": "L1 prefetcher, distance was increased"
},
{
"PublicDescription": "Level 1 prefetcher, table entry is trained",
"EventCode": "0xd60b",
"EventName": "L1_PREFETCH_ENTRY_TRAINED",
"BriefDescription": "Level 1 prefetcher, table entry is trained"
},
{
"PublicDescription": "L1 data cache refill - Read or Write",
"EventCode": "0xd60e",
"EventName": "L1D_CACHE_REFILL_RW",
"BriefDescription": "L1 data cache refill - Read or Write"
},
{
"PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",
"EventCode": "0xD701",
"EventName": "L2C_INST_REFILL",
"BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"
},
{
"PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",
"EventCode": "0xD702",
"EventName": "L2C_DATA_REFILL",
"BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"
},
{
"PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",
"EventCode": "0xD703",
"EventName": "L2_PREFETCH_REQ",
"BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"
}
]

464
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/core-imp-def.json Normal file
View File

@ -0,0 +1,464 @@
[
{
"PublicDescription": "Level 2 prefetch requests, refilled to L2 cache",
"EventCode": "0x10A",
"EventName": "L2_PREFETCH_REFILL",
"BriefDescription": "Level 2 prefetch requests, refilled to L2 cache"
},
{
"PublicDescription": "Level 2 prefetch requests, late",
"EventCode": "0x10B",
"EventName": "L2_PREFETCH_UPGRADE",
"BriefDescription": "Level 2 prefetch requests, late"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB",
"EventCode": "0x110",
"EventName": "BPU_HIT_BTB",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB",
"EventCode": "0x111",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor",
"EventCode": "0x112",
"EventName": "BPU_HIT_INDIRECT_PREDICTOR",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor",
"EventCode": "0x113",
"EventName": "BPU_HIT_RSB",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor"
},
{
"PublicDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB",
"EventCode": "0x114",
"EventName": "BPU_UNCONDITIONAL_BRANCH_MISS_BTB",
"BriefDescription": "Predictable unconditional branch speculatively executed that did not hit any level of BTB"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted",
"EventCode": "0x115",
"EventName": "BPU_BRANCH_NO_HIT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted"
},
{
"PublicDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict",
"EventCode": "0x116",
"EventName": "BPU_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed that hit any level of BTB that mispredict"
},
{
"PublicDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict",
"EventCode": "0x117",
"EventName": "BPU_CONDITIONAL_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable conditional branch speculatively executed that hit any level of BTB that (direction) mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict",
"EventCode": "0x118",
"EventName": "BPU_INDIRECT_BRANCH_HIT_BTB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the indirect predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict",
"EventCode": "0x119",
"EventName": "BPU_HIT_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the return predictor that mispredict"
},
{
"PublicDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict",
"EventCode": "0x11a",
"EventName": "BPU_MISS_RSB_AND_MISPREDICT",
"BriefDescription": "Predictable taken branch speculatively executed that hit any level of BTB that access the overflow/underflow return predictor that mispredict"
},
{
"PublicDescription": "Predictable branch speculatively executed, unpredicted, that mispredict",
"EventCode": "0x11b",
"EventName": "BPU_NO_PREDICTION_MISPREDICT",
"BriefDescription": "Predictable branch speculatively executed, unpredicted, that mispredict"
},
{
"PublicDescription": "Preditable branch update the BTB region buffer entry",
"EventCode": "0x11c",
"EventName": "BPU_BTB_UPDATE",
"BriefDescription": "Preditable branch update the BTB region buffer entry"
},
{
"PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
"EventCode": "0x11d",
"EventName": "BPU_RSB_FULL_STALL",
"BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
},
{
"PublicDescription": "Macro-ops speculatively decoded",
"EventCode": "0x11f",
"EventName": "ICF_INST_SPEC_DECODE",
"BriefDescription": "Macro-ops speculatively decoded"
},
{
"PublicDescription": "Flushes",
"EventCode": "0x120",
"EventName": "GPC_FLUSH",
"BriefDescription": "Flushes"
},
{
"PublicDescription": "Flushes due to memory hazards",
"EventCode": "0x121",
"EventName": "GPC_FLUSH_MEM_FAULT",
"BriefDescription": "Flushes due to memory hazards"
},
{
"PublicDescription": "ETM extout bit 0",
"EventCode": "0x141",
"EventName": "MSC_ETM_EXTOUT0",
"BriefDescription": "ETM extout bit 0"
},
{
"PublicDescription": "ETM extout bit 1",
"EventCode": "0x142",
"EventName": "MSC_ETM_EXTOUT1",
"BriefDescription": "ETM extout bit 1"
},
{
"PublicDescription": "ETM extout bit 2",
"EventCode": "0x143",
"EventName": "MSC_ETM_EXTOUT2",
"BriefDescription": "ETM extout bit 2"
},
{
"PublicDescription": "ETM extout bit 3",
"EventCode": "0x144",
"EventName": "MSC_ETM_EXTOUT3",
"BriefDescription": "ETM extout bit 3"
},
{
"PublicDescription": "Bus request sn",
"EventCode": "0x156",
"EventName": "L2C_SNOOP",
"BriefDescription": "Bus request sn"
},
{
"PublicDescription": "L2 TXDAT LCRD blocked",
"EventCode": "0x169",
"EventName": "L2C_DAT_CRD_STALL",
"BriefDescription": "L2 TXDAT LCRD blocked"
},
{
"PublicDescription": "L2 TXRSP LCRD blocked",
"EventCode": "0x16a",
"EventName": "L2C_RSP_CRD_STALL",
"BriefDescription": "L2 TXRSP LCRD blocked"
},
{
"PublicDescription": "L2 TXREQ LCRD blocked",
"EventCode": "0x16b",
"EventName": "L2C_REQ_CRD_STALL",
"BriefDescription": "L2 TXREQ LCRD blocked"
},
{
"PublicDescription": "Early mispredict",
"EventCode": "0xD100",
"EventName": "ICF_EARLY_MIS_PRED",
"BriefDescription": "Early mispredict"
},
{
"PublicDescription": "FEQ full cycles",
"EventCode": "0xD101",
"EventName": "ICF_FEQ_FULL",
"BriefDescription": "FEQ full cycles"
},
{
"PublicDescription": "Instruction FIFO Full",
"EventCode": "0xD102",
"EventName": "ICF_INST_FIFO_FULL",
"BriefDescription": "Instruction FIFO Full"
},
{
"PublicDescription": "L1I TLB miss",
"EventCode": "0xD103",
"EventName": "L1I_TLB_MISS",
"BriefDescription": "L1I TLB miss"
},
{
"PublicDescription": "ICF sent 0 instructions to IDR this cycle",
"EventCode": "0xD104",
"EventName": "ICF_STALL",
"BriefDescription": "ICF sent 0 instructions to IDR this cycle"
},
{
"PublicDescription": "PC FIFO Full",
"EventCode": "0xD105",
"EventName": "ICF_PC_FIFO_FULL",
"BriefDescription": "PC FIFO Full"
},
{
"PublicDescription": "Stall due to BOB ID",
"EventCode": "0xD200",
"EventName": "IDR_STALL_BOB_ID",
"BriefDescription": "Stall due to BOB ID"
},
{
"PublicDescription": "Dispatch stall due to LOB entries",
"EventCode": "0xD201",
"EventName": "IDR_STALL_LOB_ID",
"BriefDescription": "Dispatch stall due to LOB entries"
},
{
"PublicDescription": "Dispatch stall due to SOB entries",
"EventCode": "0xD202",
"EventName": "IDR_STALL_SOB_ID",
"BriefDescription": "Dispatch stall due to SOB entries"
},
{
"PublicDescription": "Dispatch stall due to IXU scheduler entries",
"EventCode": "0xD203",
"EventName": "IDR_STALL_IXU_SCHED",
"BriefDescription": "Dispatch stall due to IXU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to FSU scheduler entries",
"EventCode": "0xD204",
"EventName": "IDR_STALL_FSU_SCHED",
"BriefDescription": "Dispatch stall due to FSU scheduler entries"
},
{
"PublicDescription": "Dispatch stall due to ROB entries",
"EventCode": "0xD205",
"EventName": "IDR_STALL_ROB_ID",
"BriefDescription": "Dispatch stall due to ROB entries"
},
{
"PublicDescription": "Dispatch stall due to flush",
"EventCode": "0xD206",
"EventName": "IDR_STALL_FLUSH",
"BriefDescription": "Dispatch stall due to flush"
},
{
"PublicDescription": "Dispatch stall due to WFI",
"EventCode": "0xD207",
"EventName": "IDR_STALL_WFI",
"BriefDescription": "Dispatch stall due to WFI"
},
{
"PublicDescription": "Number of SWOB drains triggered by timeout",
"EventCode": "0xD208",
"EventName": "IDR_STALL_SWOB_TIMEOUT",
"BriefDescription": "Number of SWOB drains triggered by timeout"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
"EventCode": "0xD209",
"EventName": "IDR_STALL_SWOB_RAW",
"BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
},
{
"PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
"EventCode": "0xD20A",
"EventName": "IDR_STALL_SWOB_FULL",
"BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
},
{
"PublicDescription": "Dispatch stall due to L1 instruction cache miss",
"EventCode": "0xD20B",
"EventName": "STALL_FRONTEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 instruction cache miss"
},
{
"PublicDescription": "Dispatch stall due to L1 data cache miss",
"EventCode": "0xD20D",
"EventName": "STALL_BACKEND_CACHE",
"BriefDescription": "Dispatch stall due to L1 data cache miss"
},
{
"PublicDescription": "Dispatch stall due to lack of any core resource",
"EventCode": "0xD20F",
"EventName": "STALL_BACKEND_RESOURCE",
"BriefDescription": "Dispatch stall due to lack of any core resource"
},
{
"PublicDescription": "Instructions issued by the scheduler",
"EventCode": "0xD300",
"EventName": "IXU_NUM_UOPS_ISSUED",
"BriefDescription": "Instructions issued by the scheduler"
},
{
"PublicDescription": "Any uop issued was canceled for any reason",
"EventCode": "0xD301",
"EventName": "IXU_ISSUE_CANCEL",
"BriefDescription": "Any uop issued was canceled for any reason"
},
{
"PublicDescription": "A load wakeup to the scheduler has been canceled",
"EventCode": "0xD302",
"EventName": "IXU_LOAD_CANCEL",
"BriefDescription": "A load wakeup to the scheduler has been canceled"
},
{
"PublicDescription": "The scheduler had to cancel one slow Uop due to resource conflict",
"EventCode": "0xD303",
"EventName": "IXU_SLOW_CANCEL",
"BriefDescription": "The scheduler had to cancel one slow Uop due to resource conflict"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA",
"EventCode": "0xD304",
"EventName": "IXU_IXA_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 0",
"EventCode": "0xD305",
"EventName": "IXU_IXA_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXA Par 1",
"EventCode": "0xD306",
"EventName": "IXU_IXA_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXA Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB",
"EventCode": "0xD307",
"EventName": "IXU_IXB_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 0",
"EventCode": "0xD308",
"EventName": "IXU_IXB_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXB Par 1",
"EventCode": "0xD309",
"EventName": "IXU_IXB_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXB Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC",
"EventCode": "0xD30A",
"EventName": "IXU_IXC_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 0",
"EventCode": "0xD30B",
"EventName": "IXU_IXC_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXC Par 1",
"EventCode": "0xD30C",
"EventName": "IXU_IXC_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXC Par 1"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD",
"EventCode": "0xD30D",
"EventName": "IXU_IXD_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 0",
"EventCode": "0xD30E",
"EventName": "IXU_IXD_PAR0_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 0"
},
{
"PublicDescription": "Uops issued by the scheduler on IXD Par 1",
"EventCode": "0xD30F",
"EventName": "IXU_IXD_PAR1_ISSUED",
"BriefDescription": "Uops issued by the scheduler on IXD Par 1"
},
{
"PublicDescription": "Uops issued by the FSU scheduler",
"EventCode": "0xD400",
"EventName": "FSU_ISSUED",
"BriefDescription": "Uops issued by the FSU scheduler"
},
{
"PublicDescription": "Uops issued by the scheduler on FSX",
"EventCode": "0xD401",
"EventName": "FSU_FSX_ISSUED",
"BriefDescription": "Uops issued by the scheduler on FSX"
},
{
"PublicDescription": "Uops issued by the scheduler on FSY",
"EventCode": "0xD402",
"EventName": "FSU_FSY_ISSUED",
"BriefDescription": "Uops issued by the scheduler on FSY"
},
{
"PublicDescription": "Uops issued by the scheduler on FSZ",
"EventCode": "0xD403",
"EventName": "FSU_FSZ_ISSUED",
"BriefDescription": "Uops issued by the scheduler on FSZ"
},
{
"PublicDescription": "Uops canceled (load cancels)",
"EventCode": "0xD404",
"EventName": "FSU_CANCEL",
"BriefDescription": "Uops canceled (load cancels)"
},
{
"PublicDescription": "Count scheduler stalls due to divide/sqrt",
"EventCode": "0xD405",
"EventName": "FSU_DIV_SQRT_STALL",
"BriefDescription": "Count scheduler stalls due to divide/sqrt"
},
{
"PublicDescription": "Number of SWOB drains",
"EventCode": "0xD500",
"EventName": "GPC_SWOB_DRAIN",
"BriefDescription": "Number of SWOB drains"
},
{
"PublicDescription": "GPC detected a Breakpoint instruction match",
"EventCode": "0xD501",
"EventName": "BREAKPOINT_MATCH",
"BriefDescription": "GPC detected a Breakpoint instruction match"
},
{
"PublicDescription": "Core progress monitor triggered",
"EventCode": "0xd502",
"EventName": "GPC_CPM_TRIGGER",
"BriefDescription": "Core progress monitor triggered"
},
{
"PublicDescription": "Fill buffer full",
"EventCode": "0xD601",
"EventName": "OFB_FULL",
"BriefDescription": "Fill buffer full"
},
{
"PublicDescription": "Load satisified from store forwarded data",
"EventCode": "0xD605",
"EventName": "LD_FROM_ST_FWD",
"BriefDescription": "Load satisified from store forwarded data"
},
{
"PublicDescription": "Store retirement pipe stall",
"EventCode": "0xD60C",
"EventName": "LSU_ST_RETIRE_STALL",
"BriefDescription": "Store retirement pipe stall"
},
{
"PublicDescription": "LSU detected a Watchpoint data match",
"EventCode": "0xD60D",
"EventName": "WATCHPOINT_MATCH",
"BriefDescription": "LSU detected a Watchpoint data match"
},
{
"PublicDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTALL feature",
"EventCode": "0xda00",
"EventName": "MSC_ETM_COMMIT_STALL",
"BriefDescription": "Counts cycles that MSC is telling GPC to stall commit due to ETM ISTALL feature"
}
]

47
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[
{
"ArchStdEvent": "EXC_UNDEF"
},
{
"ArchStdEvent": "EXC_SVC"
},
{
"ArchStdEvent": "EXC_PABORT"
},
{
"ArchStdEvent": "EXC_DABORT"
},
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"ArchStdEvent": "EXC_HVC"
},
{
"ArchStdEvent": "EXC_TRAP_PABORT"
},
{
"ArchStdEvent": "EXC_TRAP_DABORT"
},
{
"ArchStdEvent": "EXC_TRAP_OTHER"
},
{
"ArchStdEvent": "EXC_TRAP_IRQ"
},
{
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"ArchStdEvent": "EXC_TAKEN"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "EXC_SMC"
}
]

128
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[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "ST_RETIRED"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "BR_IMMED_RETIRED"
},
{
"ArchStdEvent": "BR_RETURN_RETIRED"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"ArchStdEvent": "RC_LD_SPEC"
},
{
"ArchStdEvent": "RC_ST_SPEC"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "PC_WRITE_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "TTBR_WRITE_RETIRED"
},
{
"ArchStdEvent": "BR_RETIRED"
},
{
"ArchStdEvent": "BR_MIS_PRED_RETIRED"
},
{
"ArchStdEvent": "OP_RETIRED"
},
{
"ArchStdEvent": "OP_SPEC"
},
{
"PublicDescription": "Operation speculatively executed - ASE Scalar",
"EventCode": "0xd210",
"EventName": "ASE_SCALAR_SPEC",
"BriefDescription": "Operation speculatively executed - ASE Scalar"
},
{
"PublicDescription": "Operation speculatively executed - ASE Vector",
"EventCode": "0xd211",
"EventName": "ASE_VECTOR_SPEC",
"BriefDescription": "Operation speculatively executed - ASE Vector"
},
{
"PublicDescription": "Barrier speculatively executed, CSDB",
"EventCode": "0x7f",
"EventName": "CSDB_SPEC",
"BriefDescription": "Barrier speculatively executed, CSDB"
},
{
"PublicDescription": "Prefetch sent to L2.",
"EventCode": "0xd106",
"EventName": "ICF_PREFETCH_DISPATCH",
"BriefDescription": "Prefetch sent to L2."
},
{
"PublicDescription": "Prefetch response received but was dropped since we don't support inflight upgrades.",
"EventCode": "0xd107",
"EventName": "ICF_PREFETCH_DROPPED_NO_UPGRADE",
"BriefDescription": "Prefetch response received but was dropped since we don't support inflight upgrades."
},
{
"PublicDescription": "Prefetch request missed TLB.",
"EventCode": "0xd108",
"EventName": "ICF_PREFETCH_DROPPED_TLB_MISS",
"BriefDescription": "Prefetch request missed TLB."
},
{
"PublicDescription": "Prefetch request dropped since duplicate was found in TLB.",
"EventCode": "0xd109",
"EventName": "ICF_PREFETCH_DROPPED_DUPLICATE",
"BriefDescription": "Prefetch request dropped since duplicate was found in TLB."
},
{
"PublicDescription": "Prefetch request dropped since it was found in cache.",
"EventCode": "0xd10a",
"EventName": "ICF_PREFETCH_DROPPED_CACHE_HIT",
"BriefDescription": "Prefetch request dropped since it was found in cache."
}
]

14
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/intrinsic.json Normal file
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[
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_PASS_SPEC"
},
{
"ArchStdEvent": "STREX_FAIL_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
}
]

41
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/memory.json Normal file
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[
{
"ArchStdEvent": "LD_RETIRED"
},
{
"ArchStdEvent": "MEM_ACCESS_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_WR"
},
{
"ArchStdEvent": "LD_ALIGN_LAT"
},
{
"ArchStdEvent": "ST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS"
},
{
"ArchStdEvent": "MEMORY_ERROR"
},
{
"ArchStdEvent": "LDST_ALIGN_LAT"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
},
{
"ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
},
{
"PublicDescription": "Flushes due to memory hazards",
"EventCode": "0x121",
"EventName": "BPU_FLUSH_MEM_FAULT",
"BriefDescription": "Flushes due to memory hazards"
}
]

442
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json Normal file
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[
{
"MetricName": "branch_miss_pred_rate",
"MetricExpr": "BR_MIS_PRED / BR_PRED",
"BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch",
"MetricGroup": "branch",
"ScaleUnit": "100%"
},
{
"MetricName": "bus_utilization",
"MetricExpr": "BUS_ACCESS / (BUS_CYCLES * 1)",
"BriefDescription": "Core-to-uncore bus utilization",
"MetricGroup": "Bus",
"ScaleUnit": "100percent of bus cycles"
},
{
"MetricName": "l1d_cache_miss_ratio",
"MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE",
"BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.",
"MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l1i_cache_miss_ratio",
"MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE",
"BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.",
"MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "Miss_Ratio;l1d_cache_read_miss",
"MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD",
"BriefDescription": "L1D cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache read access"
},
{
"MetricName": "l2_cache_miss_ratio",
"MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE",
"BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
"MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l1i_cache_read_miss_rate",
"MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE",
"BriefDescription": "L1I cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache access"
},
{
"MetricName": "l2d_cache_read_miss_rate",
"MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD",
"BriefDescription": "L2 cache read miss rate",
"MetricGroup": "Cache",
"ScaleUnit": "1per cache read access"
},
{
"MetricName": "l1d_cache_miss_mpki",
"MetricExpr": "(L1D_CACHE_LMISS_RD * 1e3) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (data)",
"MetricGroup": "Cache",
"ScaleUnit": "1MPKI"
},
{
"MetricName": "l1i_cache_miss_mpki",
"MetricExpr": "(L1I_CACHE_LMISS * 1e3) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (instruction)",
"MetricGroup": "Cache",
"ScaleUnit": "1MPKI"
},
{
"MetricName": "simd_percentage",
"MetricExpr": "ASE_SPEC / INST_SPEC",
"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "crypto_percentage",
"MetricExpr": "CRYPTO_SPEC / INST_SPEC",
"BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "gflops",
"MetricExpr": "VFP_SPEC / (duration_time * 1e9)",
"BriefDescription": "Giga-floating point operations per second",
"MetricGroup": "InstructionMix"
},
{
"MetricName": "integer_dp_percentage",
"MetricExpr": "DP_SPEC / INST_SPEC",
"BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "ipc",
"MetricExpr": "INST_RETIRED / CPU_CYCLES",
"BriefDescription": "This metric measures the number of instructions retired per cycle.",
"MetricGroup": "General",
"ScaleUnit": "1per cycle"
},
{
"MetricName": "load_percentage",
"MetricExpr": "LD_SPEC / INST_SPEC",
"BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "load_store_spec_rate",
"MetricExpr": "LDST_SPEC / INST_SPEC",
"BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speclatively executed",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "retired_mips",
"MetricExpr": "INST_RETIRED / (duration_time * 1e6)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "InstructionMix"
},
{
"MetricName": "spec_utilization_mips",
"MetricExpr": "INST_SPEC / (duration_time * 1e6)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "PEutilization"
},
{
"MetricName": "pc_write_spec_rate",
"MetricExpr": "PC_WRITE_SPEC / INST_SPEC",
"BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speclatively executed",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "store_percentage",
"MetricExpr": "ST_SPEC / INST_SPEC",
"BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "scalar_fp_percentage",
"MetricExpr": "VFP_SPEC / INST_SPEC",
"BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.",
"MetricGroup": "Operation_Mix",
"ScaleUnit": "100percent of operations"
},
{
"MetricName": "retired_rate",
"MetricExpr": "OP_RETIRED / OP_SPEC",
"BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "wasted",
"MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))",
"BriefDescription": "Of all the micro-operations issued, what proportion are lost",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "wasted_rate",
"MetricExpr": "1 - OP_RETIRED / OP_SPEC",
"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)",
"MetricGroup": "General",
"ScaleUnit": "100%"
},
{
"MetricName": "stall_backend_cache_rate",
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_backend_resource_rate",
"MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_backend_tlb_rate",
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_frontend_cache_rate",
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_frontend_tlb_rate",
"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
"MetricGroup": "Stall",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "dtlb_walk_ratio",
"MetricExpr": "DTLB_WALK / L1D_TLB",
"BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.",
"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
"ScaleUnit": "1per TLB access"
},
{
"MetricName": "itlb_walk_ratio",
"MetricExpr": "ITLB_WALK / L1I_TLB",
"BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.",
"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
"ScaleUnit": "1per TLB access"
},
{
"ArchStdEvent": "backend_bound"
},
{
"ArchStdEvent": "frontend_bound",
"MetricExpr": "100 - (retired_fraction + slots_lost_misspeculation_fraction + backend_bound)"
},
{
"MetricName": "slots_lost_misspeculation_fraction",
"MetricExpr": "(OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots)",
"BriefDescription": "Fraction of slots lost due to misspeculation",
"DefaultMetricgroupName": "TopdownL1",
"MetricGroup": "Default;TopdownL1",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "retired_fraction",
"MetricExpr": "OP_RETIRED / (CPU_CYCLES * #slots)",
"BriefDescription": "Fraction of slots retiring, useful work",
"DefaultMetricgroupName": "TopdownL1",
"MetricGroup": "Default;TopdownL1",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "backend_core",
"MetricExpr": "(backend_bound / 100) - backend_memory",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_memory",
"MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE) / CPU_CYCLES",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100%"
},
{
"MetricName": "branch_mispredict",
"MetricExpr": "(BR_MIS_PRED_RETIRED / GPC_FLUSH) * slots_lost_misspeculation_fraction",
"BriefDescription": "Fraction of slots lost due to branch misprediciton",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "frontend_bandwidth",
"MetricExpr": "frontend_bound - frontend_latency",
"BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "frontend_latency",
"MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - ((frontend_bound / 100) * CPU_CYCLES * #slots)) / #slots)) / CPU_CYCLES",
"BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch",
"MetricGroup": "TopdownL2",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "other_miss_pred",
"MetricExpr": "slots_lost_misspeculation_fraction - branch_mispredict",
"BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "pipe_utilization",
"MetricExpr": "100 * ((IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6))",
"BriefDescription": "Fraction of execute slots utilized",
"MetricGroup": "TopdownL2",
"ScaleUnit": "1percent of slots"
},
{
"MetricName": "d_cache_l2_miss_rate",
"MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "d_cache_miss_rate",
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "d_tlb_miss_rate",
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "fsu_pipe_utilization",
"MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)",
"BriefDescription": "Fraction of FSU execute slots utilized",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "i_cache_miss_rate",
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "i_tlb_miss_rate",
"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "ixu_pipe_utilization",
"MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES * #slots)",
"BriefDescription": "Fraction of IXU execute slots utilized",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "stall_recovery_rate",
"MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery",
"MetricGroup": "TopdownL3",
"ScaleUnit": "100percent of slots"
},
{
"MetricName": "stall_fsu_sched_rate",
"MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_ixu_sched_rate",
"MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_lob_id_rate",
"MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_rob_id_rate",
"MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "stall_sob_id_rate",
"MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full",
"MetricGroup": "TopdownL4",
"ScaleUnit": "100percent of cycles"
},
{
"MetricName": "l1d_cache_access_demand",
"MetricExpr": "L1D_CACHE_RW / L1D_CACHE",
"BriefDescription": "L1D cache access - demand",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache acceses"
},
{
"MetricName": "l1d_cache_access_prefetces",
"MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE",
"BriefDescription": "L1D cache access - prefetch",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache acceses"
},
{
"MetricName": "l1d_cache_demand_misses",
"MetricExpr": "L1D_CACHE_REFILL_RW / L1D_CACHE",
"BriefDescription": "L1D cache demand misses",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache acceses"
},
{
"MetricName": "l1d_cache_demand_misses_read",
"MetricExpr": "L1D_CACHE_REFILL_RD / L1D_CACHE",
"BriefDescription": "L1D cache demand misses - read",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache acceses"
},
{
"MetricName": "l1d_cache_demand_misses_write",
"MetricExpr": "L1D_CACHE_REFILL_WR / L1D_CACHE",
"BriefDescription": "L1D cache demand misses - write",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache acceses"
},
{
"MetricName": "l1d_cache_prefetch_misses",
"MetricExpr": "L1D_CACHE_REFILL_PRFM / L1D_CACHE",
"BriefDescription": "L1D cache prefetch misses",
"MetricGroup": "Cache",
"ScaleUnit": "100percent of cache acceses"
},
{
"MetricName": "ase_scalar_mix",
"MetricExpr": "ASE_SCALAR_SPEC / OP_SPEC",
"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) scalar operations",
"MetricGroup": "Instructions",
"ScaleUnit": "100percent of cache acceses"
},
{
"MetricName": "ase_vector_mix",
"MetricExpr": "ASE_VECTOR_SPEC / OP_SPEC",
"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) vector operations",
"MetricGroup": "Instructions",
"ScaleUnit": "100percent of cache acceses"
}
]

170
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json Normal file
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[
{
"PublicDescription": "Level 2 data translation buffer allocation",
"EventCode": "0xD800",
"EventName": "MMU_D_OTB_ALLOC",
"BriefDescription": "Level 2 data translation buffer allocation"
},
{
"PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
"EventCode": "0xd801",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
"EventCode": "0xd802",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
"EventCode": "0xd803",
"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
"EventCode": "0xd804",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
"EventCode": "0xd805",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescrition": "Data TLB translation cache hit on S2L0 walk cache entry",
"EventCode": "0xd806",
"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "Data TLB translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescrition": "Data-side S1 page walk cache lookup",
"EventCode": "0xd807",
"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "Data-side S1 page walk cache lookup"
},
{
"PublicDescrition": "Data-side S1 page walk cache refill",
"EventCode": "0xd808",
"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
"BriefDescription": "Data-side S1 page walk cache refill"
},
{
"PublicDescrition": "Data-side S2 page walk cache lookup",
"EventCode": "0xd809",
"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "Data-side S2 page walk cache lookup"
},
{
"PublicDescrition": "Data-side S2 page walk cache refill",
"EventCode": "0xd80a",
"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
"BriefDescription": "Data-side S2 page walk cache refill"
},
{
"PublicDescription": "Data-side S1 table walk fault",
"EventCode": "0xD80B",
"EventName": "MMU_D_S1_WALK_FAULT",
"BriefDescription": "Data-side S1 table walk fault"
},
{
"PublicDescription": "Data-side S2 table walk fault",
"EventCode": "0xD80C",
"EventName": "MMU_D_S2_WALK_FAULT",
"BriefDescription": "Data-side S2 table walk fault"
},
{
"PublicDescription": "Data-side table walk steps or descriptor fetches",
"EventCode": "0xD80D",
"EventName": "MMU_D_WALK_STEPS",
"BriefDescription": "Data-side table walk steps or descriptor fetches"
},
{
"PublicDescription": "Level 2 instruction translation buffer allocation",
"EventCode": "0xD900",
"EventName": "MMU_I_OTB_ALLOC",
"BriefDescription": "Level 2 instruction translation buffer allocation"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S1L2 walk cache entry",
"EventCode": "0xd901",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S1L1 walk cache entry",
"EventCode": "0xd902",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S1L0 walk cache entry",
"EventCode": "0xd903",
"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S2L2 walk cache entry",
"EventCode": "0xd904",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S2L1 walk cache entry",
"EventCode": "0xd905",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry"
},
{
"PublicDescrition": "Instruction TLB translation cache hit on S2L0 walk cache entry",
"EventCode": "0xd906",
"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
"BriefDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry"
},
{
"PublicDescrition": "Instruction-side S1 page walk cache lookup",
"EventCode": "0xd907",
"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
"BriefDescription": "Instruction-side S1 page walk cache lookup"
},
{
"PublicDescrition": "Instruction-side S1 page walk cache refill",
"EventCode": "0xd908",
"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
"BriefDescription": "Instruction-side S1 page walk cache refill"
},
{
"PublicDescrition": "Instruction-side S2 page walk cache lookup",
"EventCode": "0xd909",
"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
"BriefDescription": "Instruction-side S2 page walk cache lookup"
},
{
"PublicDescrition": "Instruction-side S2 page walk cache refill",
"EventCode": "0xd90a",
"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
"BriefDescription": "Instruction-side S2 page walk cache refill"
},
{
"PublicDescription": "Instruction-side S1 table walk fault",
"EventCode": "0xD90B",
"EventName": "MMU_I_S1_WALK_FAULT",
"BriefDescription": "Instruction-side S1 table walk fault"
},
{
"PublicDescription": "Instruction-side S2 table walk fault",
"EventCode": "0xD90C",
"EventName": "MMU_I_S2_WALK_FAULT",
"BriefDescription": "Instruction-side S2 table walk fault"
},
{
"PublicDescription": "Instruction-side table walk steps or descriptor fetches",
"EventCode": "0xD90D",
"EventName": "MMU_I_WALK_STEPS",
"BriefDescription": "Instruction-side table walk steps or descriptor fetches"
}
]

41
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/pipeline.json Normal file
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@ -0,0 +1,41 @@
[
{
"ArchStdEvent": "STALL_FRONTEND",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_BACKEND"
},
{
"ArchStdEvent": "STALL",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_SLOT_BACKEND"
},
{
"ArchStdEvent": "STALL_SLOT_FRONTEND",
"Errata": "Errata AC03_CPU_29",
"BriefDescription": "Impacted by errata, use metrics instead -"
},
{
"ArchStdEvent": "STALL_SLOT"
},
{
"ArchStdEvent": "STALL_BACKEND_MEM"
},
{
"PublicDescription": "Frontend stall cycles, TLB",
"EventCode": "0x815c",
"EventName": "STALL_FRONTEND_TLB",
"BriefDescription": "Frontend stall cycles, TLB"
},
{
"PublicDescription": "Backend stall cycles, TLB",
"EventCode": "0x8167",
"EventName": "STALL_BACKEND_TLB",
"BriefDescription": "Backend stall cycles, TLB"
}
]

14
tools/perf/pmu-events/arch/arm64/ampere/ampereonex/spe.json Normal file
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[
{
"ArchStdEvent": "SAMPLE_POP"
},
{
"ArchStdEvent": "SAMPLE_FEED"
},
{
"ArchStdEvent": "SAMPLE_FILTRATE"
},
{
"ArchStdEvent": "SAMPLE_COLLISION"
}
]

1
tools/perf/pmu-events/arch/arm64/mapfile.csv
View File

@ -42,3 +42,4 @@
0x00000000480fd010,v1,hisilicon/hip08,core
0x00000000500f0000,v1,ampere/emag,core
0x00000000c00fac30,v1,ampere/ampereone,core
0x00000000c00fac40,v1,ampere/ampereonex,core

1 # Format:
42 0x00000000480fd010,v1,hisilicon/hip08,core
43 0x00000000500f0000,v1,ampere/emag,core
44 0x00000000c00fac30,v1,ampere/ampereone,core
45 0x00000000c00fac40,v1,ampere/ampereonex,core