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perf/x86/intel/uncore: Add Sapphire Rapids server UPI support 

Sapphire Rapids uses a coherent interconnect for scaling to multiple
sockets known as Intel UPI. Intel UPI technology provides a cache
coherent socket to socket external communication interface between
processors.

The layout of the control registers for a UPI uncore unit is similar to
a M2M uncore unit.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-10-git-send-email-kan.liang@linux.intel.com
This commit is contained in:
Kan Liang 2021-06-30 14:08:33 -07:00 committed by Peter Zijlstra
parent f57191edaa
commit da5a9156cd
1 changed files with 6 additions and 1 deletions
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7
arch/x86/events/intel/uncore_snbep.c
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@ -5698,6 +5698,11 @@ static struct intel_uncore_type spr_uncore_m2m = {
.name = "m2m",
};
static struct intel_uncore_type spr_uncore_upi = {
SPR_UNCORE_PCI_COMMON_FORMAT(),
.name = "upi",
};
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@ -5709,7 +5714,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
NULL,
&spr_uncore_imc,
&spr_uncore_m2m,
NULL,
&spr_uncore_upi,
NULL,
NULL,
NULL,