media: dvb-frontends/stv0910: rework and fix DiSEqC send
Rework both DiSEqC send functions (send_master_cmd() and send_burst()) to
utilise the new SET_REG() and SET_FIELD() macros. Esp. due to SET_FIELD(),
this makes sure that not all bits (with unrelated purposes) are always
rewritten, but only those needed for sending DiSEqC commands. In
send_burst(), this makes sure that DISEQC_MODE isn't changed from 3 to 2
inbetween when sending SEC_MINI_A. Also, change both functions to write
DISEQC_MODE first before setting DIS_PRECHARGE. This makes diseqc control
work more reliable for "fullblown" DiSEqC strings in VDR's diseqc.conf in
combination with certain multiswitches.
Fixes: 448461af0e
("media: dvb-frontends/stv0910: implement diseqc_send_burst")
Reported-by: Helmut Auer <post@helmutauer.de>
Cc: Ralph Metzler <rjkm@metzlerbros.de>
Signed-off-by: Daniel Scheller <d.scheller@gmx.net>
Tested-by: Helmut Auer <post@helmutauer.de>
Tested-by: Richard Scobie <rascobie@slingshot.co.nz>
Tested-by: Dietmar Spingler <d_spingler@freenet.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
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@ -1673,15 +1673,15 @@ static int send_master_cmd(struct dvb_frontend *fe,
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struct dvb_diseqc_master_cmd *cmd)
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{
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struct stv *state = fe->demodulator_priv;
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u16 offs = state->nr ? 0x40 : 0;
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int i;
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write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E);
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SET_FIELD(DISEQC_MODE, 2);
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SET_FIELD(DIS_PRECHARGE, 1);
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for (i = 0; i < cmd->msg_len; i++) {
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wait_dis(state, 0x40, 0x00);
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write_reg(state, RSTV0910_P1_DISTXFIFO + offs, cmd->msg[i]);
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SET_REG(DISTXFIFO, cmd->msg[i]);
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}
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write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A);
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SET_FIELD(DIS_PRECHARGE, 0);
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wait_dis(state, 0x20, 0x20);
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return 0;
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}
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@ -1689,19 +1689,20 @@ static int send_master_cmd(struct dvb_frontend *fe,
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static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
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{
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struct stv *state = fe->demodulator_priv;
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u16 offs = state->nr ? 0x40 : 0;
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u8 value;
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if (burst == SEC_MINI_A) {
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write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3F);
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SET_FIELD(DISEQC_MODE, 3);
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value = 0x00;
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} else {
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write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E);
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SET_FIELD(DISEQC_MODE, 2);
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value = 0xFF;
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}
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SET_FIELD(DIS_PRECHARGE, 1);
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wait_dis(state, 0x40, 0x00);
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write_reg(state, RSTV0910_P1_DISTXFIFO + offs, value);
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write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A);
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SET_REG(DISTXFIFO, value);
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SET_FIELD(DIS_PRECHARGE, 0);
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wait_dis(state, 0x20, 0x20);
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return 0;
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