serial: 8250_pci: Intel MID UART support to its own driver
Intel MID UART quirks require already quite a bit of code in 8250_pci.c. On new Intel platforms where it is used, the integrated DMA engine no longer has its own PCI device, but is instead configured from the UART's MMIO. That means we will have to add even more code for handling just MID UARTs. Instead of adding that to 8250_pci.c, splitting the support of Intel MID UART into its own driver. Handling of the integrated DMA engine becomes much simpler this way. Own driver will also remove the need for things like specific set_termios hooks for every board using this UART, and simplify the handling of it in general. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Heikki Krogerus
Greg Kroah-Hartman
parent
1d59b382f1
commit
d9eda9bab2
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@ -0,0 +1,258 @@
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/*
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* 8250_mid.c - Driver for UART on Intel Penwell and various other Intel SOCs
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*
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* Copyright (C) 2015 Intel Corporation
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* Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/rational.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/dma/hsu.h>
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#include "8250.h"
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#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
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#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
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#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
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#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
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/* Intel MID Specific registers */
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#define INTEL_MID_UART_PS 0x30
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#define INTEL_MID_UART_MUL 0x34
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#define INTEL_MID_UART_DIV 0x38
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struct mid8250;
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struct mid8250_board {
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unsigned long freq;
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unsigned int base_baud;
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int (*setup)(struct mid8250 *, struct uart_port *p);
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};
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struct mid8250 {
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int line;
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int dma_index;
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struct pci_dev *dma_dev;
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struct uart_8250_dma dma;
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struct mid8250_board *board;
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};
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/*****************************************************************************/
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static int pnw_setup(struct mid8250 *mid, struct uart_port *p)
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{
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struct pci_dev *pdev = to_pci_dev(p->dev);
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_PNW_UART1:
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mid->dma_index = 0;
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break;
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case PCI_DEVICE_ID_INTEL_PNW_UART2:
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mid->dma_index = 1;
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break;
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case PCI_DEVICE_ID_INTEL_PNW_UART3:
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mid->dma_index = 2;
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break;
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default:
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return -EINVAL;
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}
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mid->dma_dev = pci_get_slot(pdev->bus,
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PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
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return 0;
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}
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static int tng_setup(struct mid8250 *mid, struct uart_port *p)
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{
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struct pci_dev *pdev = to_pci_dev(p->dev);
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int index = PCI_FUNC(pdev->devfn);
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/* Currently no support for HSU port0 */
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if (index-- == 0)
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return -ENODEV;
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mid->dma_index = index;
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mid->dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
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return 0;
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}
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/*****************************************************************************/
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static void mid8250_set_termios(struct uart_port *p,
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struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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struct mid8250 *mid = p->private_data;
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unsigned short ps = 16;
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unsigned long fuart = baud * ps;
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unsigned long w = BIT(24) - 1;
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unsigned long mul, div;
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if (mid->board->freq < fuart) {
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/* Find prescaler value that satisfies Fuart < Fref */
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if (mid->board->freq > baud)
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ps = mid->board->freq / baud; /* baud rate too high */
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else
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ps = 1; /* PLL case */
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fuart = baud * ps;
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} else {
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/* Get Fuart closer to Fref */
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fuart *= rounddown_pow_of_two(mid->board->freq / fuart);
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}
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rational_best_approximation(fuart, mid->board->freq, w, w, &mul, &div);
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p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
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writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
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writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
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writel(div, p->membase + INTEL_MID_UART_DIV);
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serial8250_do_set_termios(p, termios, old);
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}
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static bool mid8250_dma_filter(struct dma_chan *chan, void *param)
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{
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struct hsu_dma_slave *s = param;
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if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
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return false;
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chan->private = s;
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return true;
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}
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static int mid8250_dma_setup(struct mid8250 *mid, struct uart_8250_port *port)
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{
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struct uart_8250_dma *dma = &mid->dma;
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struct device *dev = port->port.dev;
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struct hsu_dma_slave *rx_param;
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struct hsu_dma_slave *tx_param;
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rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
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if (!rx_param)
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return -ENOMEM;
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tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
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if (!tx_param)
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return -ENOMEM;
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rx_param->chan_id = mid->dma_index * 2 + 1;
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tx_param->chan_id = mid->dma_index * 2;
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dma->rxconf.src_maxburst = 64;
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dma->txconf.dst_maxburst = 64;
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rx_param->dma_dev = &mid->dma_dev->dev;
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tx_param->dma_dev = &mid->dma_dev->dev;
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dma->fn = mid8250_dma_filter;
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dma->rx_param = rx_param;
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dma->tx_param = tx_param;
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port->dma = dma;
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return 0;
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}
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static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct uart_8250_port uart;
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struct mid8250 *mid;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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pci_set_master(pdev);
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mid = devm_kzalloc(&pdev->dev, sizeof(*mid), GFP_KERNEL);
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if (!mid)
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return -ENOMEM;
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mid->board = (struct mid8250_board *)id->driver_data;
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memset(&uart, 0, sizeof(struct uart_8250_port));
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uart.port.dev = &pdev->dev;
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uart.port.irq = pdev->irq;
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uart.port.private_data = mid;
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uart.port.type = PORT_16750;
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uart.port.iotype = UPIO_MEM;
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uart.port.uartclk = mid->board->base_baud * 16;
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uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
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uart.port.set_termios = mid8250_set_termios;
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uart.port.mapbase = pci_resource_start(pdev, 0);
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uart.port.membase = pcim_iomap(pdev, 0, 0);
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if (!uart.port.membase)
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return -ENOMEM;
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if (mid->board->setup) {
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ret = mid->board->setup(mid, &uart.port);
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if (ret)
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return ret;
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}
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ret = mid8250_dma_setup(mid, &uart);
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if (ret)
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return ret;
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ret = serial8250_register_8250_port(&uart);
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if (ret < 0)
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return ret;
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mid->line = ret;
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pci_set_drvdata(pdev, mid);
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return 0;
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}
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static void mid8250_remove(struct pci_dev *pdev)
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{
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struct mid8250 *mid = pci_get_drvdata(pdev);
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serial8250_unregister_port(mid->line);
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}
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static const struct mid8250_board pnw_board = {
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.freq = 50000000,
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.base_baud = 115200,
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.setup = pnw_setup,
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};
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static const struct mid8250_board tng_board = {
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.freq = 38400000,
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.base_baud = 1843200,
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.setup = tng_setup,
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};
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#define MID_DEVICE(id, board) { PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&board }
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static const struct pci_device_id pci_ids[] = {
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MID_DEVICE(PCI_DEVICE_ID_INTEL_PNW_UART1, pnw_board),
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MID_DEVICE(PCI_DEVICE_ID_INTEL_PNW_UART2, pnw_board),
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MID_DEVICE(PCI_DEVICE_ID_INTEL_PNW_UART3, pnw_board),
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MID_DEVICE(PCI_DEVICE_ID_INTEL_TNG_UART, tng_board),
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{ },
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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static struct pci_driver mid8250_pci_driver = {
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.name = "8250_mid",
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.id_table = pci_ids,
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.probe = mid8250_probe,
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.remove = mid8250_remove,
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};
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module_pci_driver(mid8250_pci_driver);
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel MID UART driver");
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@ -28,7 +28,6 @@
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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#include <linux/platform_data/dma-hsu.h>
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#include "8250.h"
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@ -1508,167 +1507,6 @@ byt_serial_setup(struct serial_private *priv,
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return ret;
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}
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#define INTEL_MID_UART_PS 0x30
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#define INTEL_MID_UART_MUL 0x34
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#define INTEL_MID_UART_DIV 0x38
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static void intel_mid_set_termios(struct uart_port *p,
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struct ktermios *termios,
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struct ktermios *old,
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unsigned long fref)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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unsigned short ps = 16;
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unsigned long fuart = baud * ps;
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unsigned long w = BIT(24) - 1;
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unsigned long mul, div;
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if (fref < fuart) {
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/* Find prescaler value that satisfies Fuart < Fref */
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if (fref > baud)
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ps = fref / baud; /* baud rate too high */
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else
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ps = 1; /* PLL case */
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fuart = baud * ps;
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} else {
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/* Get Fuart closer to Fref */
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fuart *= rounddown_pow_of_two(fref / fuart);
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}
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rational_best_approximation(fuart, fref, w, w, &mul, &div);
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p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
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writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
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writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
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writel(div, p->membase + INTEL_MID_UART_DIV);
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serial8250_do_set_termios(p, termios, old);
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}
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static void intel_mid_set_termios_38_4M(struct uart_port *p,
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struct ktermios *termios,
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struct ktermios *old)
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{
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intel_mid_set_termios(p, termios, old, 38400000);
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}
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static void intel_mid_set_termios_50M(struct uart_port *p,
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struct ktermios *termios,
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struct ktermios *old)
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{
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/*
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* The uart clk is 50Mhz, and the baud rate come from:
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* baud = 50M * MUL / (DIV * PS * DLAB)
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*/
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intel_mid_set_termios(p, termios, old, 50000000);
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}
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static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
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{
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struct hsu_dma_slave *s = param;
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if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
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return false;
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chan->private = s;
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return true;
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}
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static int intel_mid_serial_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx,
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int index, struct pci_dev *dma_dev)
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{
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struct device *dev = port->port.dev;
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struct uart_8250_dma *dma;
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struct hsu_dma_slave *tx_param, *rx_param;
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dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return -ENOMEM;
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tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
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if (!tx_param)
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return -ENOMEM;
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rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
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if (!rx_param)
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return -ENOMEM;
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rx_param->chan_id = index * 2 + 1;
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tx_param->chan_id = index * 2;
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dma->rxconf.src_maxburst = 64;
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dma->txconf.dst_maxburst = 64;
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rx_param->dma_dev = &dma_dev->dev;
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tx_param->dma_dev = &dma_dev->dev;
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dma->fn = intel_mid_dma_filter;
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dma->rx_param = rx_param;
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dma->tx_param = tx_param;
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port->port.type = PORT_16750;
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port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
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port->dma = dma;
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return pci_default_setup(priv, board, port, idx);
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}
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#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
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#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
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#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
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static int pnw_serial_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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{
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struct pci_dev *pdev = priv->dev;
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struct pci_dev *dma_dev;
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int index;
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_PNW_UART1:
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index = 0;
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break;
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case PCI_DEVICE_ID_INTEL_PNW_UART2:
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index = 1;
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break;
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case PCI_DEVICE_ID_INTEL_PNW_UART3:
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index = 2;
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break;
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default:
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return -EINVAL;
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}
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dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
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port->port.set_termios = intel_mid_set_termios_50M;
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return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
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}
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#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
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static int tng_serial_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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{
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struct pci_dev *pdev = priv->dev;
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struct pci_dev *dma_dev;
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int index = PCI_FUNC(pdev->devfn);
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/* Currently no support for HSU port0 */
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if (index-- == 0)
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return -ENODEV;
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dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
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port->port.set_termios = intel_mid_set_termios_38_4M;
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return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
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}
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static int
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pci_omegapci_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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@ -2210,34 +2048,6 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.subdevice = PCI_ANY_ID,
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.setup = byt_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PNW_UART1,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pnw_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PNW_UART2,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pnw_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PNW_UART3,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
|
||||
.setup = pnw_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_TNG_UART,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = tng_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_BSW_UART1,
|
||||
|
|
@ -3119,8 +2929,6 @@ enum pci_board_num_t {
|
|||
pbn_ADDIDATA_PCIe_8_3906250,
|
||||
pbn_ce4100_1_115200,
|
||||
pbn_byt,
|
||||
pbn_pnw,
|
||||
pbn_tng,
|
||||
pbn_qrk,
|
||||
pbn_omegapci,
|
||||
pbn_NETMOS9900_2s_115200,
|
||||
|
|
@ -3907,16 +3715,6 @@ static struct pciserial_board pci_boards[] = {
|
|||
.uart_offset = 0x80,
|
||||
.reg_shift = 2,
|
||||
},
|
||||
[pbn_pnw] = {
|
||||
.flags = FL_BASE0,
|
||||
.num_ports = 1,
|
||||
.base_baud = 115200,
|
||||
},
|
||||
[pbn_tng] = {
|
||||
.flags = FL_BASE0,
|
||||
.num_ports = 1,
|
||||
.base_baud = 1843200,
|
||||
},
|
||||
[pbn_qrk] = {
|
||||
.flags = FL_BASE0,
|
||||
.num_ports = 1,
|
||||
|
|
@ -4005,6 +3803,12 @@ static const struct pci_device_id blacklist[] = {
|
|||
{ PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
|
||||
{ PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
|
||||
{ PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
|
||||
|
||||
/* Intel platforms with MID UART */
|
||||
{ PCI_VDEVICE(INTEL, 0x081b), },
|
||||
{ PCI_VDEVICE(INTEL, 0x081c), },
|
||||
{ PCI_VDEVICE(INTEL, 0x081d), },
|
||||
{ PCI_VDEVICE(INTEL, 0x1191), },
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -5701,26 +5505,6 @@ static struct pci_device_id serial_pci_tbl[] = {
|
|||
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
|
||||
pbn_byt },
|
||||
|
||||
/*
|
||||
* Intel Penwell
|
||||
*/
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
pbn_pnw},
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
pbn_pnw},
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
pbn_pnw},
|
||||
|
||||
/*
|
||||
* Intel Tangier
|
||||
*/
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
pbn_tng},
|
||||
|
||||
/*
|
||||
* Intel Quark x1000
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -367,3 +367,11 @@ config SERIAL_8250_INGENIC
|
|||
help
|
||||
If you have a system using an Ingenic SoC and wish to make use of
|
||||
its UARTs, say Y to this option. If unsure, say N.
|
||||
|
||||
config SERIAL_8250_MID
|
||||
tristate "Support for serial ports on Intel MID platforms"
|
||||
depends on SERIAL_8250 && PCI
|
||||
help
|
||||
Selecting this option will enable handling of the extra features
|
||||
present on the UART found on Intel Medfield SOC and various other
|
||||
Intel platforms.
|
||||
|
|
|
|||
|
|
@ -27,5 +27,6 @@ obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o
|
|||
obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o
|
||||
obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o
|
||||
obj-$(CONFIG_SERIAL_8250_INGENIC) += 8250_ingenic.o
|
||||
obj-$(CONFIG_SERIAL_8250_MID) += 8250_mid.o
|
||||
|
||||
CFLAGS_8250_ingenic.o += -I$(srctree)/scripts/dtc/libfdt
|
||||
|
|
|
|||
Loading…
Reference in New Issue