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arm64: dts: juno: Enable more SMMUs 

Now that PCI inbound window restrictions are handled generically between
the of_pci resource parsing and the IOMMU layer, and described in the
Juno DT, we can finally enable the PCIe SMMU without the risk of DMA
mappings inadvertently allocating unusable addresses.

Similarly, the relevant support for IOMMU mappings for peripheral
transfers has been hooked up in the pl330 driver for ages, so we can
happily enable the DMA SMMU without that breaking anything either.

Link: https://lore.kernel.org/r/a730070d718cb119f77c8ca1782a0d4189bfb3e7.1614965598.git.robin.murphy@arm.com
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Robin Murphy 2021-03-05 17:33:18 +00:00 committed by Sudeep Holla
parent 4ac4d146cb
commit d9df28ba58
3 changed files with 8 additions and 1 deletions
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1
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -644,7 +644,6 @@
#iommu-cells = <1>; #iommu-cells = <1>;
#global-interrupts = <1>; #global-interrupts = <1>;
dma-coherent; dma-coherent;
status = "disabled";
}; };
smmu_hdlcd1: iommu@7fb10000 { smmu_hdlcd1: iommu@7fb10000 {

4
arch/arm64/boot/dts/arm/juno-r1.dts
View File

@ -230,6 +230,10 @@
status = "okay"; status = "okay";
}; };
&smmu_pcie {
status = "okay";
};
&etm0 { &etm0 {
cpu = <&A57_0>; cpu = <&A57_0>;
}; };

4
arch/arm64/boot/dts/arm/juno-r2.dts
View File

@ -236,6 +236,10 @@
status = "okay"; status = "okay";
}; };
&smmu_pcie {
status = "okay";
};
&etm0 { &etm0 {
cpu = <&A72_0>; cpu = <&A72_0>;
}; };