UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

intel_rapl: support 64 bit register 

RAPL MMIO interface uses 64 bit registers, thus force use 64 bit register
for all the RAPL code.

Reviewed-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com>
Tested-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Zhang Rui 2019-07-10 21:44:31 +08:00 committed by Rafael J. Wysocki
parent 3382388d71
commit d978e755aa
3 changed files with 14 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/powercap/intel_rapl_common.c
View File

@ -689,7 +689,7 @@ static int rapl_read_data_raw(struct rapl_domain *rd,
ra.mask = rp->mask; ra.mask = rp->mask;
if (rd->rp->priv->read_raw(cpu, &ra)) { if (rd->rp->priv->read_raw(cpu, &ra)) {
pr_debug("failed to read reg 0x%x on cpu %d\n", ra.reg, cpu); pr_debug("failed to read reg 0x%llx on cpu %d\n", ra.reg, cpu);
return -EIO; return -EIO;
} }
@ -749,7 +749,7 @@ static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
ra.reg = rp->priv->reg_unit; ra.reg = rp->priv->reg_unit;
ra.mask = ~0; ra.mask = ~0;
if (rp->priv->read_raw(cpu, &ra)) { if (rp->priv->read_raw(cpu, &ra)) {
pr_err("Failed to read power unit REG 0x%x on CPU %d, exit.\n", pr_err("Failed to read power unit REG 0x%llx on CPU %d, exit.\n",
rp->priv->reg_unit, cpu); rp->priv->reg_unit, cpu);
return -ENODEV; return -ENODEV;
} }
@ -777,7 +777,7 @@ static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
ra.reg = rp->priv->reg_unit; ra.reg = rp->priv->reg_unit;
ra.mask = ~0; ra.mask = ~0;
if (rp->priv->read_raw(cpu, &ra)) { if (rp->priv->read_raw(cpu, &ra)) {
pr_err("Failed to read power unit REG 0x%x on CPU %d, exit.\n", pr_err("Failed to read power unit REG 0x%llx on CPU %d, exit.\n",
rp->priv->reg_unit, cpu); rp->priv->reg_unit, cpu);
return -ENODEV; return -ENODEV;
} }

11
drivers/powercap/intel_rapl_msr.c
View File

@ -84,8 +84,10 @@ static int rapl_cpu_down_prep(unsigned int cpu)
static int rapl_msr_read_raw(int cpu, struct reg_action *ra) static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
{ {
if (rdmsrl_safe_on_cpu(cpu, ra->reg, &ra->value)) { u32 msr = (u32)ra->reg;
pr_debug("failed to read msr 0x%x on cpu %d\n", ra->reg, cpu);
if (rdmsrl_safe_on_cpu(cpu, msr, &ra->value)) {
pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
return -EIO; return -EIO;
} }
ra->value &= ra->mask; ra->value &= ra->mask;
@ -95,16 +97,17 @@ static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
static void rapl_msr_update_func(void *info) static void rapl_msr_update_func(void *info)
{ {
struct reg_action *ra = info; struct reg_action *ra = info;
u32 msr = (u32)ra->reg;
u64 val; u64 val;
ra->err = rdmsrl_safe(ra->reg, &val); ra->err = rdmsrl_safe(msr, &val);
if (ra->err) if (ra->err)
return; return;
val &= ~ra->mask; val &= ~ra->mask;
val |= ra->value; val |= ra->value;
ra->err = wrmsrl_safe(ra->reg, val); ra->err = wrmsrl_safe(msr, val);
} }
static int rapl_msr_write_raw(int cpu, struct reg_action *ra) static int rapl_msr_write_raw(int cpu, struct reg_action *ra)

8
include/linux/intel_rapl.h
View File

@ -78,7 +78,7 @@ struct rapl_package;
struct rapl_domain { struct rapl_domain {
const char *name; const char *name;
enum rapl_domain_type id; enum rapl_domain_type id;
int regs[RAPL_DOMAIN_REG_MAX]; u64 regs[RAPL_DOMAIN_REG_MAX];
struct powercap_zone power_zone; struct powercap_zone power_zone;
struct rapl_domain_data rdd; struct rapl_domain_data rdd;
struct rapl_power_limit rpl[NR_POWER_LIMITS]; struct rapl_power_limit rpl[NR_POWER_LIMITS];
@ -89,7 +89,7 @@ struct rapl_domain {
}; };
struct reg_action { struct reg_action {
u32 reg; u64 reg;
u64 mask; u64 mask;
u64 value; u64 value;
int err; int err;
@ -113,8 +113,8 @@ struct rapl_if_priv {
struct powercap_control_type *control_type; struct powercap_control_type *control_type;
struct rapl_domain *platform_rapl_domain; struct rapl_domain *platform_rapl_domain;
enum cpuhp_state pcap_rapl_online; enum cpuhp_state pcap_rapl_online;
u32 reg_unit; u64 reg_unit;
u32 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX]; u64 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX];
int (*read_raw)(int cpu, struct reg_action *ra); int (*read_raw)(int cpu, struct reg_action *ra);
int (*write_raw)(int cpu, struct reg_action *ra); int (*write_raw)(int cpu, struct reg_action *ra);
}; };