ARM: imx: remove deprecated symbols as all users are gone now
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This commit is contained in:
Uwe Kleine-König
parent
ac401427c0
commit
d96801b2ca
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@ -165,131 +165,4 @@
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*/
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#define USBD_INT0 MX1_USBD_INT0
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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/* these should go away */
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#define IMX_IO_PHYS MX1_IO_BASE_ADDR
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#define IMX_IO_SIZE MX1_IO_SIZE
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#define IMX_CS0_PHYS MX1_CS0_PHYS
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#define IMX_CS0_SIZE MX1_CS0_SIZE
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#define IMX_CS1_PHYS MX1_CS1_PHYS
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#define IMX_CS1_SIZE MX1_CS1_SIZE
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#define IMX_CS2_PHYS MX1_CS2_PHYS
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#define IMX_CS2_SIZE MX1_CS2_SIZE
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#define IMX_CS3_PHYS MX1_CS3_PHYS
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#define IMX_CS3_SIZE MX1_CS3_SIZE
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#define IMX_CS4_PHYS MX1_CS4_PHYS
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#define IMX_CS4_SIZE MX1_CS4_SIZE
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#define IMX_CS5_PHYS MX1_CS5_PHYS
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#define IMX_CS5_SIZE MX1_CS5_SIZE
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#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
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#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
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#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
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#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
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#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
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#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
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#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
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#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
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#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
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#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
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#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
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#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
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#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
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#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
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#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
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#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
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#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
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#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
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#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
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#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
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#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
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#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
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#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
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#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
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#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
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#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
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#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
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#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
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#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
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#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
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#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
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#define INT_SOFTINT MX1_INT_SOFTINT
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#define CSI_INT MX1_CSI_INT
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#define DSPA_MAC_INT MX1_DSPA_MAC_INT
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#define DSPA_INT MX1_DSPA_INT
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#define COMP_INT MX1_COMP_INT
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#define MSHC_XINT MX1_MSHC_XINT
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#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
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#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
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#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
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#define LCDC_INT MX1_LCDC_INT
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#define SIM_INT MX1_SIM_INT
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#define SIM_DATA_INT MX1_SIM_DATA_INT
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#define RTC_INT MX1_RTC_INT
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#define RTC_SAMINT MX1_RTC_SAMINT
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#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
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#define UART2_MINT_RTS MX1_UART2_MINT_RTS
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#define UART2_MINT_DTR MX1_UART2_MINT_DTR
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#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
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#define UART2_MINT_TX MX1_UART2_MINT_TX
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#define UART2_MINT_RX MX1_UART2_MINT_RX
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#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
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#define UART1_MINT_RTS MX1_UART1_MINT_RTS
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#define UART1_MINT_DTR MX1_UART1_MINT_DTR
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#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
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#define UART1_MINT_TX MX1_UART1_MINT_TX
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#define UART1_MINT_RX MX1_UART1_MINT_RX
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#define VOICE_DAC_INT MX1_VOICE_DAC_INT
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#define VOICE_ADC_INT MX1_VOICE_ADC_INT
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#define PEN_DATA_INT MX1_PEN_DATA_INT
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#define PWM_INT MX1_PWM_INT
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#define SDHC_INT MX1_SDHC_INT
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#define I2C_INT MX1_INT_I2C
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#define CSPI_INT MX1_CSPI_INT
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#define SSI_TX_INT MX1_SSI_TX_INT
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#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
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#define SSI_RX_INT MX1_SSI_RX_INT
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#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
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#define TOUCH_INT MX1_TOUCH_INT
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#define USBD_INT1 MX1_USBD_INT1
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#define USBD_INT2 MX1_USBD_INT2
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#define USBD_INT3 MX1_USBD_INT3
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#define USBD_INT4 MX1_USBD_INT4
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#define USBD_INT5 MX1_USBD_INT5
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#define USBD_INT6 MX1_USBD_INT6
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#define BTSYS_INT MX1_BTSYS_INT
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#define BTTIM_INT MX1_BTTIM_INT
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#define BTWUI_INT MX1_BTWUI_INT
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#define TIM2_INT MX1_TIM2_INT
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#define TIM1_INT MX1_TIM1_INT
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#define DMA_ERR MX1_DMA_ERR
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#define DMA_INT MX1_DMA_INT
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#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
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#define WDT_INT MX1_WDT_INT
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#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
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#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
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#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
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#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
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#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
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#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
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#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
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#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
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#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
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#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
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#define DMA_REQ_EXT MX1_DMA_REQ_EXT
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#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
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#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
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#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
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#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
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#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
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#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
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#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
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#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
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#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
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#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
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#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
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#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
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#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
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#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
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#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
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#endif /* ifndef __MACH_MX1_H__ */
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@ -179,38 +179,4 @@
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#define MX21_DMA_REQ_CSI_STAT 30
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#define MX21_DMA_REQ_CSI_RX 31
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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/* these should go away */
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#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
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#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
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#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
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#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
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#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
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#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
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#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
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#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
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#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
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#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
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#define X_MEMC_SIZE MX21_X_MEMC_SIZE
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#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
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#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
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#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
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#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
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#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
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#define MXC_INT_FIRI MX21_INT_FIRI
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#define MXC_INT_BMI MX21_INT_BMI
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#define MXC_INT_EMMAENC MX21_INT_EMMAENC
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#define MXC_INT_EMMADEC MX21_INT_EMMADEC
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#define MXC_INT_USBWKUP MX21_INT_USBWKUP
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#define MXC_INT_USBDMA MX21_INT_USBDMA
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#define MXC_INT_USBHOST MX21_INT_USBHOST
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#define MXC_INT_USBFUNC MX21_INT_USBFUNC
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#define MXC_INT_USBMNP MX21_INT_USBMNP
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#define MXC_INT_USBCTRL MX21_INT_USBCTRL
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#define MXC_INT_USBCTRL MX21_INT_USBCTRL
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#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
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#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
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#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
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#endif
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#endif /* ifndef __MACH_MX21_H__ */
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@ -244,73 +244,4 @@ static inline void mx27_setup_weimcs(size_t cs,
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extern int mx27_revision(void);
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#endif
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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/* these should go away */
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#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
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#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
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#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
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#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
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#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
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#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
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#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
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#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
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#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
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#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
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#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
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#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
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#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
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#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
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#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
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#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
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#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
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#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
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#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
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#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
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#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
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#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
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#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
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#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
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#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
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#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
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#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
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#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
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#define X_MEMC_SIZE MX27_X_MEMC_SIZE
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#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
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#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
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#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
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#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
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#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
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#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
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#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
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#define MXC_INT_I2C2 MX27_INT_I2C2
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#define MXC_INT_GPT6 MX27_INT_GPT6
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#define MXC_INT_GPT5 MX27_INT_GPT5
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#define MXC_INT_GPT4 MX27_INT_GPT4
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#define MXC_INT_RTIC MX27_INT_RTIC
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#define MXC_INT_SDHC MX27_INT_SDHC
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#define MXC_INT_SDHC3 MX27_INT_SDHC3
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#define MXC_INT_ATA MX27_INT_ATA
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#define MXC_INT_UART6 MX27_INT_UART6
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#define MXC_INT_UART5 MX27_INT_UART5
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#define MXC_INT_FEC MX27_INT_FEC
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#define MXC_INT_VPU MX27_INT_VPU
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#define MXC_INT_USB1 MX27_INT_USB1
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#define MXC_INT_USB2 MX27_INT_USB2
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#define MXC_INT_USB3 MX27_INT_USB3
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#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
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#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
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#define MXC_INT_SAHARA MX27_INT_SAHARA
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#define MXC_INT_IIM MX27_INT_IIM
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#define MXC_INT_CCM MX27_INT_CCM
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#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
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#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
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#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
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#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
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#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
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#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
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#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
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#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
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#define DMA_REQ_NFC MX27_DMA_REQ_NFC
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#endif
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#endif /* ifndef __MACH_MX27_H__ */
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@ -141,116 +141,4 @@
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#define MX2x_DMA_REQ_CSI_STAT 30
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#define MX2x_DMA_REQ_CSI_RX 31
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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/* these should go away */
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#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
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#define AIPI_SIZE MX2x_AIPI_SIZE
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#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
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#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
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#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
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#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
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#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
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#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
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#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
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#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
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#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
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#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
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#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
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#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
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#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
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#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
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#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
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#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
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#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
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#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
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#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
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#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
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#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
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#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
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#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
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#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
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#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
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#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
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#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
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#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
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#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
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#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
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#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
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#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
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#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
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#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
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#define SAHB1_SIZE MX2x_SAHB1_SIZE
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#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
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#define MXC_INT_CSPI3 MX2x_INT_CSPI3
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#define MXC_INT_GPIO MX2x_INT_GPIO
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#define MXC_INT_SDHC2 MX2x_INT_SDHC2
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#define MXC_INT_SDHC1 MX2x_INT_SDHC1
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#define MXC_INT_I2C MX2x_INT_I2C
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#define MXC_INT_SSI2 MX2x_INT_SSI2
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#define MXC_INT_SSI1 MX2x_INT_SSI1
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#define MXC_INT_CSPI2 MX2x_INT_CSPI2
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#define MXC_INT_CSPI1 MX2x_INT_CSPI1
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#define MXC_INT_UART4 MX2x_INT_UART4
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#define MXC_INT_UART3 MX2x_INT_UART3
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#define MXC_INT_UART2 MX2x_INT_UART2
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#define MXC_INT_UART1 MX2x_INT_UART1
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#define MXC_INT_KPP MX2x_INT_KPP
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#define MXC_INT_RTC MX2x_INT_RTC
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#define MXC_INT_PWM MX2x_INT_PWM
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#define MXC_INT_GPT3 MX2x_INT_GPT3
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#define MXC_INT_GPT2 MX2x_INT_GPT2
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#define MXC_INT_GPT1 MX2x_INT_GPT1
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#define MXC_INT_WDOG MX2x_INT_WDOG
|
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#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
|
||||
#define MXC_INT_NANDFC MX2x_INT_NANDFC
|
||||
#define MXC_INT_CSI MX2x_INT_CSI
|
||||
#define MXC_INT_DMACH0 MX2x_INT_DMACH0
|
||||
#define MXC_INT_DMACH1 MX2x_INT_DMACH1
|
||||
#define MXC_INT_DMACH2 MX2x_INT_DMACH2
|
||||
#define MXC_INT_DMACH3 MX2x_INT_DMACH3
|
||||
#define MXC_INT_DMACH4 MX2x_INT_DMACH4
|
||||
#define MXC_INT_DMACH5 MX2x_INT_DMACH5
|
||||
#define MXC_INT_DMACH6 MX2x_INT_DMACH6
|
||||
#define MXC_INT_DMACH7 MX2x_INT_DMACH7
|
||||
#define MXC_INT_DMACH8 MX2x_INT_DMACH8
|
||||
#define MXC_INT_DMACH9 MX2x_INT_DMACH9
|
||||
#define MXC_INT_DMACH10 MX2x_INT_DMACH10
|
||||
#define MXC_INT_DMACH11 MX2x_INT_DMACH11
|
||||
#define MXC_INT_DMACH12 MX2x_INT_DMACH12
|
||||
#define MXC_INT_DMACH13 MX2x_INT_DMACH13
|
||||
#define MXC_INT_DMACH14 MX2x_INT_DMACH14
|
||||
#define MXC_INT_DMACH15 MX2x_INT_DMACH15
|
||||
#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
|
||||
#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
|
||||
#define MXC_INT_SLCDC MX2x_INT_SLCDC
|
||||
#define MXC_INT_LCDC MX2x_INT_LCDC
|
||||
#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
|
||||
#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
|
||||
#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
|
||||
#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
|
||||
#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
|
||||
#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
|
||||
#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
|
||||
#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
|
||||
#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
|
||||
#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
|
||||
#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
|
||||
#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
|
||||
#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
|
||||
#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
|
||||
#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
|
||||
#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
|
||||
#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
|
||||
#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
|
||||
#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
|
||||
#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
|
||||
#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
|
||||
#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
|
||||
#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
|
||||
#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
|
||||
#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
|
||||
#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
|
||||
#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __MACH_MX2x_H__ */
|
||||
|
|
|
|||
|
|
@ -215,36 +215,4 @@ static inline void mx31_setup_weimcs(size_t cs,
|
|||
#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
|
||||
#define MX31_SYSTEM_REV_NUM 3
|
||||
|
||||
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
|
||||
/* these should go away */
|
||||
#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
|
||||
#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
|
||||
#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
|
||||
#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
|
||||
#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
|
||||
#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
|
||||
#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
|
||||
#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
|
||||
#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
|
||||
#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
|
||||
#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
|
||||
#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
|
||||
#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
|
||||
#define MXC_INT_FIRI MX31_INT_FIRI
|
||||
#define MXC_INT_MBX MX31_INT_MBX
|
||||
#define MXC_INT_CSPI3 MX31_INT_CSPI3
|
||||
#define MXC_INT_SIM2 MX31_INT_SIM2
|
||||
#define MXC_INT_SIM1 MX31_INT_SIM1
|
||||
#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
|
||||
#define MXC_INT_USB1 MX31_INT_USB1
|
||||
#define MXC_INT_USB2 MX31_INT_USB2
|
||||
#define MXC_INT_USB3 MX31_INT_USB3
|
||||
#define MXC_INT_USB4 MX31_INT_USB4
|
||||
#define MXC_INT_MSHC2 MX31_INT_MSHC2
|
||||
#define MXC_INT_UART4 MX31_INT_UART4
|
||||
#define MXC_INT_UART5 MX31_INT_UART5
|
||||
#define MXC_INT_CCM MX31_INT_CCM
|
||||
#define MXC_INT_PCMCIA MX31_INT_PCMCIA
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __MACH_MX31_H__ */
|
||||
|
|
|
|||
|
|
@ -183,20 +183,4 @@
|
|||
#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
|
||||
#define MX35_SYSTEM_REV_NUM 3
|
||||
|
||||
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
|
||||
/* these should go away */
|
||||
#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
|
||||
#define MXC_INT_OWIRE MX35_INT_OWIRE
|
||||
#define MXC_INT_GPU2D MX35_INT_GPU2D
|
||||
#define MXC_INT_ASRC MX35_INT_ASRC
|
||||
#define MXC_INT_USBHS MX35_INT_USBHS
|
||||
#define MXC_INT_USBOTG MX35_INT_USBOTG
|
||||
#define MXC_INT_ESAI MX35_INT_ESAI
|
||||
#define MXC_INT_CAN1 MX35_INT_CAN1
|
||||
#define MXC_INT_CAN2 MX35_INT_CAN2
|
||||
#define MXC_INT_MLB MX35_INT_MLB
|
||||
#define MXC_INT_SPDIF MX35_INT_SPDIF
|
||||
#define MXC_INT_FEC MX35_INT_FEC
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __MACH_MX35_H__ */
|
||||
|
|
|
|||
|
|
@ -221,118 +221,4 @@ static inline int mx35_revision(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
|
||||
/* these should go away */
|
||||
#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
|
||||
#define L2CC_SIZE MX3x_L2CC_SIZE
|
||||
#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
|
||||
#define AIPS1_SIZE MX3x_AIPS1_SIZE
|
||||
#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
|
||||
#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
|
||||
#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
|
||||
#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
|
||||
#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
|
||||
#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
|
||||
#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
|
||||
#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
|
||||
#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
|
||||
#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
|
||||
#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
|
||||
#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
|
||||
#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
|
||||
#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
|
||||
#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
|
||||
#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
|
||||
#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
|
||||
#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
|
||||
#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
|
||||
#define SPBA0_SIZE MX3x_SPBA0_SIZE
|
||||
#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
|
||||
#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
|
||||
#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
|
||||
#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
|
||||
#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
|
||||
#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
|
||||
#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
|
||||
#define AIPS2_SIZE MX3x_AIPS2_SIZE
|
||||
#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
|
||||
#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
|
||||
#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
|
||||
#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
|
||||
#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
|
||||
#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
|
||||
#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
|
||||
#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
|
||||
#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
|
||||
#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
|
||||
#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
|
||||
#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
|
||||
#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
|
||||
#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
|
||||
#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
|
||||
#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
|
||||
#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
|
||||
#define ROMP_SIZE MX3x_ROMP_SIZE
|
||||
#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
|
||||
#define AVIC_SIZE MX3x_AVIC_SIZE
|
||||
#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
|
||||
#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
|
||||
#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
|
||||
#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
|
||||
#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
|
||||
#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
|
||||
#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
|
||||
#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
|
||||
#define CS4_SIZE MX3x_CS4_SIZE
|
||||
#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
|
||||
#define CS5_SIZE MX3x_CS5_SIZE
|
||||
#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
|
||||
#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
|
||||
#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
|
||||
#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
|
||||
#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
|
||||
#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
|
||||
#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
|
||||
#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
|
||||
#define MXC_INT_I2C3 MX3x_INT_I2C3
|
||||
#define MXC_INT_I2C2 MX3x_INT_I2C2
|
||||
#define MXC_INT_RTIC MX3x_INT_RTIC
|
||||
#define MXC_INT_I2C MX3x_INT_I2C
|
||||
#define MXC_INT_CSPI2 MX3x_INT_CSPI2
|
||||
#define MXC_INT_CSPI1 MX3x_INT_CSPI1
|
||||
#define MXC_INT_ATA MX3x_INT_ATA
|
||||
#define MXC_INT_UART3 MX3x_INT_UART3
|
||||
#define MXC_INT_IIM MX3x_INT_IIM
|
||||
#define MXC_INT_RNGA MX3x_INT_RNGA
|
||||
#define MXC_INT_EVTMON MX3x_INT_EVTMON
|
||||
#define MXC_INT_KPP MX3x_INT_KPP
|
||||
#define MXC_INT_RTC MX3x_INT_RTC
|
||||
#define MXC_INT_PWM MX3x_INT_PWM
|
||||
#define MXC_INT_EPIT2 MX3x_INT_EPIT2
|
||||
#define MXC_INT_EPIT1 MX3x_INT_EPIT1
|
||||
#define MXC_INT_GPT MX3x_INT_GPT
|
||||
#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
|
||||
#define MXC_INT_UART2 MX3x_INT_UART2
|
||||
#define MXC_INT_NANDFC MX3x_INT_NANDFC
|
||||
#define MXC_INT_SDMA MX3x_INT_SDMA
|
||||
#define MXC_INT_MSHC1 MX3x_INT_MSHC1
|
||||
#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
|
||||
#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
|
||||
#define MXC_INT_UART1 MX3x_INT_UART1
|
||||
#define MXC_INT_ECT MX3x_INT_ECT
|
||||
#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
|
||||
#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
|
||||
#define MXC_INT_GPIO2 MX3x_INT_GPIO2
|
||||
#define MXC_INT_GPIO1 MX3x_INT_GPIO1
|
||||
#define MXC_INT_WDOG MX3x_INT_WDOG
|
||||
#define MXC_INT_GPIO3 MX3x_INT_GPIO3
|
||||
#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
|
||||
#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
|
||||
#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
|
||||
#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
|
||||
#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
|
||||
#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
|
||||
#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __MACH_MX3x_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue