[SCSI] pm8001: Add FUNC_GET_EVENTS
Jack noticed I dropped a patch fragment associated with a flags automatic variable in mpi_set_phys_g3_with_ssc (ooops) and that the pre-emptive locking that piggy-backed this patch was not in-fact necessary because of underlying atomic accesses to the hardware. Here is the updated patch fixing these two issues. The pm8001 driver is missing the FUNC_GET_EVENTS handler in the phy control function. Since the pm8001_bar4_shift function was not designed to be called at runtime, added locking surrounding the adjustment for all accesses. Signed-off-by: Mark Salyzyn <mark_salyzyn@xyratex.com> Acked-by: Jack Wang <jack_wang@usish.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Mark Salyzyn
James Bottomley
parent
5c4fb76af3
commit
d95d00016f
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@ -338,26 +338,25 @@ update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
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}
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/**
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* bar4_shift - function is called to shift BAR base address
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* @pm8001_ha : our hba card information
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* pm8001_bar4_shift - function is called to shift BAR base address
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* @pm8001_ha : our hba card infomation
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* @shiftValue : shifting value in memory bar.
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*/
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static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
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int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
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{
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u32 regVal;
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u32 max_wait_count;
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unsigned long start;
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/* program the inbound AXI translation Lower Address */
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pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
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/* confirm the setting is written */
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max_wait_count = 1 * 1000 * 1000; /* 1 sec */
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start = jiffies + HZ; /* 1 sec */
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do {
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udelay(1);
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regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
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} while ((regVal != shiftValue) && (--max_wait_count));
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} while ((regVal != shiftValue) && time_before(jiffies, start));
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if (!max_wait_count) {
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if (regVal != shiftValue) {
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
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" = 0x%x\n", regVal));
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@ -375,6 +374,7 @@ static void __devinit
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mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
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{
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u32 value, offset, i;
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unsigned long flags;
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#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
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#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
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@ -388,16 +388,23 @@ mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
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* Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
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* Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
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*/
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if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
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spin_lock_irqsave(&pm8001_ha->lock, flags);
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if (-1 == pm8001_bar4_shift(pm8001_ha,
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SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return;
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}
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for (i = 0; i < 4; i++) {
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offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
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pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
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}
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/* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
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if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
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if (-1 == pm8001_bar4_shift(pm8001_ha,
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SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return;
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}
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for (i = 4; i < 8; i++) {
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offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
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pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
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@ -421,7 +428,8 @@ mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
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pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
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/*set the shifted destination address to 0x0 to avoid error operation */
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bar4_shift(pm8001_ha, 0x0);
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pm8001_bar4_shift(pm8001_ha, 0x0);
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return;
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}
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@ -437,6 +445,7 @@ mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
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u32 offset;
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u32 value;
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u32 i;
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unsigned long flags;
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#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
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#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
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@ -445,24 +454,30 @@ mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
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#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
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value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
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spin_lock_irqsave(&pm8001_ha->lock, flags);
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/* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
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if (-1 == bar4_shift(pm8001_ha,
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OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
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if (-1 == pm8001_bar4_shift(pm8001_ha,
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OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return;
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}
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for (i = 0; i < 4; i++) {
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offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
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pm8001_cw32(pm8001_ha, 2, offset, value);
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}
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if (-1 == bar4_shift(pm8001_ha,
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OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
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if (-1 == pm8001_bar4_shift(pm8001_ha,
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OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return;
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}
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for (i = 4; i < 8; i++) {
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offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
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pm8001_cw32(pm8001_ha, 2, offset, value);
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}
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/*set the shifted destination address to 0x0 to avoid error operation */
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bar4_shift(pm8001_ha, 0x0);
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pm8001_bar4_shift(pm8001_ha, 0x0);
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return;
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}
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@ -688,8 +703,11 @@ static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk("Firmware is ready for reset .\n"));
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} else {
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unsigned long flags;
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/* Trigger NMI twice via RB6 */
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if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
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spin_lock_irqsave(&pm8001_ha->lock, flags);
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if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("Shift Bar4 to 0x%x failed\n",
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RB6_ACCESS_REG));
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@ -715,8 +733,10 @@ static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return -1;
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}
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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}
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return 0;
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}
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@ -733,6 +753,7 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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u32 regVal, toggleVal;
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u32 max_wait_count;
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u32 regVal1, regVal2, regVal3;
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unsigned long flags;
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/* step1: Check FW is ready for soft reset */
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if (soft_reset_ready_check(pm8001_ha) != 0) {
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@ -743,7 +764,9 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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/* step 2: clear NMI status register on AAP1 and IOP, write the same
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value to clear */
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/* map 0x60000 to BAR4(0x20), BAR2(win) */
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if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
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spin_lock_irqsave(&pm8001_ha->lock, flags);
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if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("Shift Bar4 to 0x%x failed\n",
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MBIC_AAP1_ADDR_BASE));
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@ -754,7 +777,8 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
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pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
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/* map 0x70000 to BAR4(0x20), BAR2(win) */
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if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
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if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("Shift Bar4 to 0x%x failed\n",
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MBIC_IOP_ADDR_BASE));
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@ -796,7 +820,8 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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/* read required registers for confirmming */
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/* map 0x0700000 to BAR4(0x20), BAR2(win) */
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if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
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if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("Shift Bar4 to 0x%x failed\n",
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GSM_ADDR_BASE));
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@ -862,7 +887,8 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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/* step 5: delay 10 usec */
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udelay(10);
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/* step 5-b: set GPIO-0 output control to tristate anyway */
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if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
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if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk("Shift Bar4 to 0x%x failed\n",
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GPIO_ADDR_BASE));
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@ -878,7 +904,8 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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/* Step 6: Reset the IOP and AAP1 */
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/* map 0x00000 to BAR4(0x20), BAR2(win) */
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if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
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if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
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SPC_TOP_LEVEL_ADDR_BASE));
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@ -915,7 +942,8 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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/* step 11: reads and sets the GSM Configuration and Reset Register */
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/* map 0x0700000 to BAR4(0x20), BAR2(win) */
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if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
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if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
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GSM_ADDR_BASE));
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@ -968,7 +996,8 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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/* step 13: bring the IOP and AAP1 out of reset */
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/* map 0x00000 to BAR4(0x20), BAR2(win) */
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if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
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if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("Shift Bar4 to 0x%x failed\n",
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SPC_TOP_LEVEL_ADDR_BASE));
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@ -1010,6 +1039,7 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
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pm8001_cr32(pm8001_ha, 0,
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MSGU_SCRATCH_PAD_3)));
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return -1;
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}
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@ -1039,9 +1069,12 @@ pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
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pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
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pm8001_cr32(pm8001_ha, 0,
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MSGU_SCRATCH_PAD_3)));
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return -1;
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}
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}
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pm8001_bar4_shift(pm8001_ha, 0);
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk("SPC soft reset Complete\n"));
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@ -1157,8 +1190,8 @@ pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
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msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
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msi_index += MSIX_TABLE_BASE;
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pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
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}
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/**
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* pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
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* @pm8001_ha: our hba card information
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@ -166,6 +166,7 @@ int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
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struct pm8001_hba_info *pm8001_ha = NULL;
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struct sas_phy_linkrates *rates;
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DECLARE_COMPLETION_ONSTACK(completion);
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unsigned long flags;
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pm8001_ha = sas_phy->ha->lldd_ha;
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pm8001_ha->phy[phy_id].enable_completion = &completion;
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switch (func) {
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@ -209,8 +210,29 @@ int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
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case PHY_FUNC_DISABLE:
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PM8001_CHIP_DISP->phy_stop_req(pm8001_ha, phy_id);
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break;
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case PHY_FUNC_GET_EVENTS:
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spin_lock_irqsave(&pm8001_ha->lock, flags);
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if (-1 == pm8001_bar4_shift(pm8001_ha,
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(phy_id < 4) ? 0x30000 : 0x40000)) {
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return -EINVAL;
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}
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{
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struct sas_phy *phy = sas_phy->phy;
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uint32_t *qp = (uint32_t *)(((char *)
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pm8001_ha->io_mem[2].memvirtaddr)
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+ 0x1034 + (0x4000 * (phy_id & 3)));
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phy->invalid_dword_count = qp[0];
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phy->running_disparity_error_count = qp[1];
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phy->loss_of_dword_sync_count = qp[3];
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phy->phy_reset_problem_count = qp[4];
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}
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pm8001_bar4_shift(pm8001_ha, 0);
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spin_unlock_irqrestore(&pm8001_ha->lock, flags);
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return 0;
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default:
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rc = -ENOSYS;
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rc = -EOPNOTSUPP;
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}
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msleep(300);
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return rc;
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@ -488,6 +488,7 @@ int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
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dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
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u32 mem_size, u32 align);
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int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
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/* ctl shared API */
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extern struct device_attribute *pm8001_host_attrs[];
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