RISC-V Devicetrees for v6.5 Part 2
T-Head: Add a basic dtsi, Kconfig bits & trivial binding additions for the T-Head 1520 SoC (codename "light"). This SoC can be found on the Lichee Pi 4a, for which a minimal dts is added. Misc: Re-sort the dts Makefile to be in alphanumerical order by directory. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZJDOAwAKCRB4tDGHoIJi 0gAoAQCqGDPqdw5MdT/+tTJqkAIVFo3KyxSrMHvv3TE36Xp1HgEAxJQ+NoZ30nhx pbaJaRcZDw7PKOVmMJ92R564EMdjngA= =hJMo -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSSFO4ACgkQYKtH/8kJ UiekuA//UW0YV5dUVykYY7EAB9ERnRfnD8S9SaaRQ+rvlZLLfceqcsGqHeB1f5nA cb4mRcS47PgTZLBpS7ZaURXFaQtJMEqFKwC/y7cjsssuXq+Vr2jf3apEL2F8IVA3 EQGTBPA9AA2+L+hSnVNCqjJP86H8y4+RuWiADUTHG9tmPrMMwHaUdL/og7Bk4zps jmBfZ6oD7upRS9+elwIInB+YH4dEnbty4VgVjJzL2PtGIS2V0zkSG+lmCv4JJmz8 esD4PT+4nnMBCh5LrGNxTJgn9zQyMHZ/pr1mK5n0hE+SLeZZj7DnEWKkchOJPdlk Hu31+dJMjcTdvJAATIqeiuUPJhhpRyLf+PenXUX48uc/nu5GZWFj/TL/fdSHoYG1 D0B1SNcJOtWm5Iy7fukMoV8e6Pz8EePTh7m/AtUaudCCDFwh/ju1TnbIzqs9DPtc iHYfFti7qVVQFL6YJnjpHHIK7UKJi4MguyDfKdl8RsRzT1Yhrx1aw0WqSYiY+a/z sdAzA85yZpU7TPmCw1DThE6uNp3YC5XqKmexwcZx3+cmpCF7HKxCieTqyVgsUkwg 9BxsQmReP1bego4oK7dGE914i0lkaGH/wDVlL0PPGPoCL8g9ZIfBGukN8sG62m9O sGPs2j4do28BK11Ow0OoRvVTbnoqZg0iGFJbk6DuWXtK881PfUc= =U5qO -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.5-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.5 Part 2 T-Head: Add a basic dtsi, Kconfig bits & trivial binding additions for the T-Head 1520 SoC (codename "light"). This SoC can be found on the Lichee Pi 4a, for which a minimal dts is added. Misc: Re-sort the dts Makefile to be in alphanumerical order by directory. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.5-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option dt-bindings: riscv: Add T-HEAD TH1520 board compatibles dt-bindings: timer: Add T-HEAD TH1520 clint dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Link: https://lore.kernel.org/r/20230620-fidelity-variety-60b47c889e31@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d8ece8b832
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@ -65,6 +65,7 @@ properties:
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- items:
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- enum:
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- allwinner,sun20i-d1-plic
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- thead,th1520-plic
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- const: thead,c900-plic
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- items:
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- const: sifive,plic-1.0.0
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@ -0,0 +1,29 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/thead.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: T-HEAD SoC-based boards
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maintainers:
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- Jisheng Zhang <jszhang@kernel.org>
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description:
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T-HEAD SoC-based boards
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
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items:
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- enum:
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- sipeed,lichee-pi-4a
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- const: sipeed,lichee-module-4a
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- const: thead,th1520
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additionalProperties: true
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...
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@ -37,6 +37,7 @@ properties:
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- items:
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- enum:
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- allwinner,sun20i-d1-clint
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- thead,th1520-clint
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- const: thead,c900-clint
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- items:
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- const: sifive,clint0
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@ -18163,6 +18163,14 @@ F: drivers/perf/riscv_pmu.c
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F: drivers/perf/riscv_pmu_legacy.c
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F: drivers/perf/riscv_pmu_sbi.c
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RISC-V THEAD SoC SUPPORT
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M: Jisheng Zhang <jszhang@kernel.org>
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M: Guo Ren <guoren@kernel.org>
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M: Fu Wei <wefu@redhat.com>
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L: linux-riscv@lists.infradead.org
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S: Maintained
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F: arch/riscv/boot/dts/thead/
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RNBD BLOCK DRIVERS
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M: Md. Haris Iqbal <haris.iqbal@ionos.com>
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M: Jack Wang <jinpu.wang@ionos.com>
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@ -41,6 +41,12 @@ config ARCH_SUNXI
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This enables support for Allwinner sun20i platform hardware,
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including boards based on the D1 and D1s SoCs.
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config ARCH_THEAD
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bool "T-HEAD RISC-V SoCs"
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select ERRATA_THEAD
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help
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This enables support for the RISC-V based T-HEAD SoCs.
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config ARCH_VIRT
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def_bool SOC_VIRT
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@ -1,9 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0
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subdir-y += allwinner
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subdir-y += sifive
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subdir-y += starfive
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subdir-y += canaan
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subdir-y += microchip
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subdir-y += renesas
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subdir-y += sifive
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subdir-y += starfive
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subdir-y += thead
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obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
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|
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
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@ -0,0 +1,38 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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/dts-v1/;
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#include "th1520.dtsi"
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/ {
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model = "Sipeed Lichee Module 4A";
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compatible = "sipeed,lichee-module-4a", "thead,th1520";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x00000000 0x2 0x00000000>;
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};
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};
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&osc {
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clock-frequency = <24000000>;
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};
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&osc_32k {
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clock-frequency = <32768>;
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};
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&apb_clk {
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clock-frequency = <62500000>;
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};
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&uart_sclk {
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clock-frequency = <100000000>;
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};
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&dmac0 {
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status = "okay";
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};
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include "th1520-lichee-module-4a.dtsi"
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/ {
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model = "Sipeed Lichee Pi 4A";
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compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,422 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "thead,th1520";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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c910_0: cpu@0 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <0>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_1: cpu@1 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <1>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_2: cpu@2 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <2>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_3: cpu@3 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <3>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <1048576>;
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cache-sets = <1024>;
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cache-unified;
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};
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_24m";
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#clock-cells = <0>;
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};
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osc_32k: 32k-oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_32k";
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#clock-cells = <0>;
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};
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apb_clk: apb-clk-clock {
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compatible = "fixed-clock";
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clock-output-names = "apb_clk";
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#clock-cells = <0>;
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};
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uart_sclk: uart-sclk-clock {
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compatible = "fixed-clock";
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clock-output-names = "uart_sclk";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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plic: interrupt-controller@ffd8000000 {
|
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compatible = "thead,th1520-plic", "thead,c900-plic";
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reg = <0xff 0xd8000000 0x0 0x01000000>;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
|
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riscv,ndev = <240>;
|
||||
};
|
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|
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clint: timer@ffdc000000 {
|
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compatible = "thead,th1520-clint", "thead,c900-clint";
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reg = <0xff 0xdc000000 0x0 0x00010000>;
|
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
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<&cpu1_intc 3>, <&cpu1_intc 7>,
|
||||
<&cpu2_intc 3>, <&cpu2_intc 7>,
|
||||
<&cpu3_intc 3>, <&cpu3_intc 7>;
|
||||
};
|
||||
|
||||
uart0: serial@ffe7014000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xe7014000 0x0 0x100>;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_sclk>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@ffe7f00000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xe7f00000 0x0 0x100>;
|
||||
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_sclk>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@ffe7f04000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xe7f04000 0x0 0x100>;
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_sclk>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio2: gpio@ffe7f34000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xe7f34000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@ffe7f38000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xe7f38000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@ffec005000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xec005000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@ffec006000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xec006000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2: serial@ffec010000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xec010000 0x0 0x4000>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_sclk>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac0: dma-controller@ffefc00000 {
|
||||
compatible = "snps,axi-dma-1.01a";
|
||||
reg = <0xff 0xefc00000 0x0 0x1000>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb_clk>, <&apb_clk>;
|
||||
clock-names = "core-clk", "cfgr-clk";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
snps,block-size = <65536 65536 65536 65536>;
|
||||
snps,priority = <0 1 2 3>;
|
||||
snps,dma-masters = <1>;
|
||||
snps,data-width = <4>;
|
||||
snps,axi-max-burst-len = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer0: timer@ffefc32000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc32000 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer1: timer@ffefc32014 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc32014 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer2: timer@ffefc32028 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc32028 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer3: timer@ffefc3203c {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc3203c 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@fff7f08000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xf7f08000 0x0 0x4000>;
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_sclk>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@fff7f0c000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xf7f0c000 0x0 0x4000>;
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_sclk>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer4: timer@ffffc33000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc33000 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer5: timer@ffffc33014 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc33014 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer6: timer@ffffc33028 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc33028 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer7: timer@ffffc3303c {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc3303c 0x0 0x14>;
|
||||
clocks = <&apb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ao_gpio0: gpio@fffff41000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xfff41000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
ao_gpio1: gpio@fffff52000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xfff52000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -27,6 +27,7 @@ CONFIG_EXPERT=y
|
|||
CONFIG_PROFILING=y
|
||||
CONFIG_SOC_MICROCHIP_POLARFIRE=y
|
||||
CONFIG_ARCH_RENESAS=y
|
||||
CONFIG_ARCH_THEAD=y
|
||||
CONFIG_SOC_SIFIVE=y
|
||||
CONFIG_SOC_STARFIVE=y
|
||||
CONFIG_ARCH_SUNXI=y
|
||||
|
|
|
|||
Loading…
Reference in New Issue