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Blackfin arch: add BF54x I2C/TWI TWI0 driver support 

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Bryan Wu 2007-07-25 16:58:03 +08:00
parent 2c95cd71f8
commit d8e715428f
3 changed files with 36 additions and 2 deletions
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4
drivers/i2c/busses/Kconfig
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@ -92,9 +92,9 @@ config I2C_AU1550
config I2C_BLACKFIN_TWI
tristate "Blackfin TWI I2C support"
depends on BF534 || BF536 || BF537
depends on BF534 || BF536 || BF537 || BF54x
help
This is the TWI I2C device driver for Blackfin 534/536/537.
This is the TWI I2C device driver for Blackfin 534/536/537/54x.
This driver can also be built as a module. If so, the module
will be called i2c-bfin-twi.

33
include/asm-blackfin/mach-bf548/cdefBF54x_base.h
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@ -242,6 +242,39 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
/* SPORT1 Registers */

1
include/asm-blackfin/mach-bf548/irq.h
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@ -112,6 +112,7 @@ Events (highest priority) EMU 0
#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
#define IRQ_TWI IRQ_TWI0 /* TWI Interrupt */
#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */