[POWERPC] cell: add low-level performance monitoring code
Add routines for accessing the registers and counters in the performance monitoring unit. Signed-off-by: Kevin Corry <kevcorry@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Kevin Corry
Paul Mackerras
parent
bffd4927ba
commit
d8bf96e079
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@ -1,5 +1,6 @@
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obj-$(CONFIG_PPC_CELL_NATIVE) += interrupt.o iommu.o setup.o \
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cbe_regs.o spider-pic.o pervasive.o
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cbe_regs.o spider-pic.o pervasive.o \
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pmu.o
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obj-$(CONFIG_CBE_RAS) += ras.o
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ifeq ($(CONFIG_SMP),y)
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@ -35,6 +35,11 @@
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*
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*/
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/* Macros for the pm_control register. */
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#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
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#define CBE_PM_ENABLE_PERF_MON 0x80000000
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union spe_reg {
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u64 val;
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u8 spe[8];
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@ -0,0 +1,328 @@
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/*
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* Cell Broadband Engine Performance Monitor
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*
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* (C) Copyright IBM Corporation 2001,2006
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*
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* Author:
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* David Erb (djerb@us.ibm.com)
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* Kevin Corry (kevcorry@us.ibm.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/reg.h>
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#include <asm/spu.h>
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#include "cbe_regs.h"
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#include "interrupt.h"
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#include "pmu.h"
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/*
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* When writing to write-only mmio addresses, save a shadow copy. All of the
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* registers are 32-bit, but stored in the upper-half of a 64-bit field in
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* pmd_regs.
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*/
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#define WRITE_WO_MMIO(reg, x) \
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do { \
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u32 _x = (x); \
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struct cbe_pmd_regs __iomem *pmd_regs; \
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struct cbe_pmd_shadow_regs *shadow_regs; \
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pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
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shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
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out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
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shadow_regs->reg = _x; \
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} while (0)
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#define READ_SHADOW_REG(val, reg) \
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do { \
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struct cbe_pmd_shadow_regs *shadow_regs; \
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shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
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(val) = shadow_regs->reg; \
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} while (0)
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#define READ_MMIO_UPPER32(val, reg) \
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do { \
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struct cbe_pmd_regs __iomem *pmd_regs; \
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pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
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(val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
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} while (0)
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/*
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* Physical counter registers.
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* Each physical counter can act as one 32-bit counter or two 16-bit counters.
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*/
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u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
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{
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u32 val_in_latch, val = 0;
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if (phys_ctr < NR_PHYS_CTRS) {
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READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
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/* Read the latch or the actual counter, whichever is newer. */
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if (val_in_latch & (1 << phys_ctr)) {
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READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
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} else {
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READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
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}
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}
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return val;
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}
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void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
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{
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struct cbe_pmd_shadow_regs *shadow_regs;
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u32 pm_ctrl;
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if (phys_ctr < NR_PHYS_CTRS) {
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/* Writing to a counter only writes to a hardware latch.
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* The new value is not propagated to the actual counter
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* until the performance monitor is enabled.
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*/
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WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
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pm_ctrl = cbe_read_pm(cpu, pm_control);
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if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
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/* The counters are already active, so we need to
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* rewrite the pm_control register to "re-enable"
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* the PMU.
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*/
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cbe_write_pm(cpu, pm_control, pm_ctrl);
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} else {
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shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
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shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
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}
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}
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}
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/*
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* "Logical" counter registers.
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* These will read/write 16-bits or 32-bits depending on the
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* current size of the counter. Counters 4 - 7 are always 16-bit.
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*/
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u32 cbe_read_ctr(u32 cpu, u32 ctr)
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{
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u32 val;
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u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
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val = cbe_read_phys_ctr(cpu, phys_ctr);
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if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
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val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
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return val;
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}
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void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
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{
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u32 phys_ctr;
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u32 phys_val;
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phys_ctr = ctr & (NR_PHYS_CTRS - 1);
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if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
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phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
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if (ctr < NR_PHYS_CTRS)
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val = (val << 16) | (phys_val & 0xffff);
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else
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val = (val & 0xffff) | (phys_val & 0xffff0000);
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}
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cbe_write_phys_ctr(cpu, phys_ctr, val);
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}
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/*
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* Counter-control registers.
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* Each "logical" counter has a corresponding control register.
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*/
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u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
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{
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u32 pm07_control = 0;
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if (ctr < NR_CTRS)
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READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
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return pm07_control;
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}
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void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
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{
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if (ctr < NR_CTRS)
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WRITE_WO_MMIO(pm07_control[ctr], val);
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}
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/*
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* Other PMU control registers. Most of these are write-only.
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*/
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u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
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{
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u32 val = 0;
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switch (reg) {
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case group_control:
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READ_SHADOW_REG(val, group_control);
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break;
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case debug_bus_control:
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READ_SHADOW_REG(val, debug_bus_control);
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break;
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case trace_address:
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READ_MMIO_UPPER32(val, trace_address);
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break;
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case ext_tr_timer:
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READ_SHADOW_REG(val, ext_tr_timer);
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break;
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case pm_status:
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READ_MMIO_UPPER32(val, pm_status);
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break;
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case pm_control:
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READ_SHADOW_REG(val, pm_control);
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break;
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case pm_interval:
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READ_SHADOW_REG(val, pm_interval);
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break;
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case pm_start_stop:
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READ_SHADOW_REG(val, pm_start_stop);
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break;
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}
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return val;
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}
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void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
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{
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switch (reg) {
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case group_control:
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WRITE_WO_MMIO(group_control, val);
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break;
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case debug_bus_control:
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WRITE_WO_MMIO(debug_bus_control, val);
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break;
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case trace_address:
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WRITE_WO_MMIO(trace_address, val);
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break;
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case ext_tr_timer:
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WRITE_WO_MMIO(ext_tr_timer, val);
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break;
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case pm_status:
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WRITE_WO_MMIO(pm_status, val);
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break;
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case pm_control:
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WRITE_WO_MMIO(pm_control, val);
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break;
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case pm_interval:
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WRITE_WO_MMIO(pm_interval, val);
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break;
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case pm_start_stop:
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WRITE_WO_MMIO(pm_start_stop, val);
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break;
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}
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}
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/*
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* Get/set the size of a physical counter to either 16 or 32 bits.
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*/
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u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
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{
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u32 pm_ctrl, size = 0;
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if (phys_ctr < NR_PHYS_CTRS) {
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pm_ctrl = cbe_read_pm(cpu, pm_control);
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size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
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}
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return size;
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}
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void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
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{
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u32 pm_ctrl;
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if (phys_ctr < NR_PHYS_CTRS) {
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pm_ctrl = cbe_read_pm(cpu, pm_control);
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switch (ctr_size) {
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case 16:
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pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
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break;
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case 32:
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pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
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break;
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}
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cbe_write_pm(cpu, pm_control, pm_ctrl);
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}
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}
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/*
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* Enable/disable the entire performance monitoring unit.
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* When we enable the PMU, all pending writes to counters get committed.
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*/
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void cbe_enable_pm(u32 cpu)
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{
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struct cbe_pmd_shadow_regs *shadow_regs;
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u32 pm_ctrl;
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shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
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shadow_regs->counter_value_in_latch = 0;
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pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
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cbe_write_pm(cpu, pm_control, pm_ctrl);
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}
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void cbe_disable_pm(u32 cpu)
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{
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u32 pm_ctrl;
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pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
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cbe_write_pm(cpu, pm_control, pm_ctrl);
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}
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/*
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* Reading from the trace_buffer.
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* The trace buffer is two 64-bit registers. Reading from
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* the second half automatically increments the trace_address.
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*/
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void cbe_read_trace_buffer(u32 cpu, u64 *buf)
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{
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struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
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*buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
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*buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
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}
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@ -0,0 +1,57 @@
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/*
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* Cell Broadband Engine Performance Monitor
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*
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* (C) Copyright IBM Corporation 2001,2006
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*
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* Author:
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* David Erb (djerb@us.ibm.com)
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* Kevin Corry (kevcorry@us.ibm.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __PERFMON_H__
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#define __PERFMON_H__
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enum pm_reg_name {
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group_control,
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debug_bus_control,
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trace_address,
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ext_tr_timer,
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pm_status,
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pm_control,
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pm_interval,
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pm_start_stop,
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};
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extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
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extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
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extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
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extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
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extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
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extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
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extern u32 cbe_read_pm (u32 cpu, enum pm_reg_name reg);
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extern void cbe_write_pm (u32 cpu, enum pm_reg_name reg, u32 val);
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extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
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extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
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extern void cbe_enable_pm(u32 cpu);
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extern void cbe_disable_pm(u32 cpu);
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extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
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#endif
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