Blackfin: cpufreq: use a constant latency
PLL_LOCKCNT applies only to the PLL programming sequence which does not apply to core and system clock dividers. Writes to PLL_DIV to change the CSEL/SSEL dividers take effect immediately. There is still overhead in software in writing the new dividers, so just use a value of 50us as this should be good enough. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -138,7 +138,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
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dpm_state_table[index].tscale);
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}
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policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
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policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
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/*Now ,only support one cpu */
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policy->cur = cclk;
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cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
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