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ARM: OMAP2+: Drop legacy platform data for omap4 fdif 

We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.

As we're just dropping data, and the early platform data init
is based on the custom ti,hwmods property, we want to drop both
the platform data and ti,hwmods property in a single patch.

Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2019-12-10 08:10:25 -08:00
parent 5725e6c169
commit d864dbdfa6
2 changed files with 0 additions and 63 deletions
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1
arch/arm/boot/dts/omap4-l4.dtsi
View File

@ -715,7 +715,6 @@
target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "fdif";
reg = <0xa000 0x4>,
<0xa010 0x4>;
reg-names = "rev", "sysc";

62
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -875,50 +875,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/*
* 'fdif' class
* face detection hw accelerator module
*/
static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
/*
* FDIF needs 100 OCP clk cycles delay after a softreset before
* accessing sysconfig again.
* The lowest frequency at the moment for L3 bus is 100 MHz, so
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
*
* TODO: Indicate errata when available.
*/
.srst_udelay = 2,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
.name = "fdif",
.sysc = &omap44xx_fdif_sysc,
};
/* fdif */
static struct omap_hwmod omap44xx_fdif_hwmod = {
.name = "fdif",
.class = &omap44xx_fdif_hwmod_class,
.clkdm_name = "iss_clkdm",
.main_clk = "fdif_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'gpmc' class
* general purpose memory controller
@ -1597,14 +1553,6 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* fdif -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
.master = &omap44xx_fdif_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* ipu -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
.master = &omap44xx_ipu_hwmod,
@ -1949,14 +1897,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> fdif */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_fdif_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod,
@ -2114,7 +2054,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_mpu__l3_main_1,
&omap44xx_debugss__l3_main_2,
&omap44xx_dma_system__l3_main_2,
&omap44xx_fdif__l3_main_2,
&omap44xx_ipu__l3_main_2,
&omap44xx_iss__l3_main_2,
&omap44xx_iva__l3_main_2,
@ -2157,7 +2096,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_per__dss_rfbi,
&omap44xx_l3_main_2__dss_venc,
&omap44xx_l4_per__dss_venc,
&omap44xx_l4_cfg__fdif,
&omap44xx_l3_main_2__gpmc,
&omap44xx_l3_main_2__ipu,
&omap44xx_l3_main_2__iss,