ARM: dts: r8a7744: Initial SoC device tree
Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Biju Das
Simon Horman
parent
3c248aefe7
commit
d83010f87a
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7744 SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r8a7744-cpg-mssr.h>
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#include <dt-bindings/power/r8a7744-sysc.h>
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/ {
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compatible = "renesas,r8a7744";
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#address-cells = <2>;
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#size-cells = <2>;
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency
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* clocks by default.
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* Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External CAN clock */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
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clock-latency = <300000>; /* 300 us */
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power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
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next-level-cache = <&L2_CA15>;
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1500000 1000000>,
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<1312500 1000000>,
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<1125000 1000000>,
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< 937500 1000000>,
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< 750000 1000000>,
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< 375000 1000000>;
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};
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L2_CA15: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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power-domains = <&sysc R8A7744_PD_CA15_SCU>;
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};
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};
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/* External root clock */
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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/* External PCIe clock - can be overridden by the board */
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pcie_bus_clk: pcie_bus {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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};
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/* External SCIF clock */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio0: gpio@e6050000 {
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reg = <0 0xe6050000 0 0x50>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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/* placeholder */
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};
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gpio1: gpio@e6051000 {
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reg = <0 0xe6051000 0 0x50>;
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#gpio-cells = <2>;
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/* placeholder */
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};
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gpio2: gpio@e6052000 {
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reg = <0 0xe6052000 0 0x50>;
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#gpio-cells = <2>;
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/* placeholder */
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};
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gpio6: gpio@e6055400 {
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reg = <0 0xe6055400 0 0x50>;
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#gpio-cells = <2>;
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/* placeholder */
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7744";
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reg = <0 0xe6060000 0 0x250>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7744-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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clock-names = "extal", "usb_extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7744-rst";
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reg = <0 0xe6160000 0 0x100>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7744-sysc";
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reg = <0 0xe6180000 0 0x200>;
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#power-domain-cells = <1>;
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};
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icram0: sram@e63a0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63a0000 0 0x12000>;
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};
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icram1: sram@e63c0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63c0000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xe63c0000 0x1000>;
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smp-sram@0 {
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compatible = "renesas,smp-sram";
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reg = <0 0x100>;
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};
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};
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icram2: sram@e6300000 {
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compatible = "mmio-sram";
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reg = <0 0xe6300000 0 0x40000>;
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};
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i2c2: i2c@e6530000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0xe6530000 0 0x40>;
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/* placeholder */
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};
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i2c5: i2c@e6528000 {
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/* doesn't need pinmux */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0xe6528000 0 0x40>;
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/* placeholder */
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};
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hsusb: usb@e6590000 {
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reg = <0 0xe6590000 0 0x100>;
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/* placeholder */
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};
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usbphy: usb-phy@e6590100 {
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reg = <0 0xe6590100 0 0x100>;
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/* placeholder */
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};
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avb: ethernet@e6800000 {
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reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* placeholder */
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};
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scifb1: serial@e6c30000 {
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reg = <0 0xe6c30000 0 0x100>;
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/* placeholder */
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7744",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6e60000 0 0x40>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 721>,
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<&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
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resets = <&cpg 721>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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reg = <0 0xe6e68000 0 0x40>;
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/* placeholder */
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};
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hscif1: serial@e62c8000 {
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reg = <0 0xe62c8000 0 0x60>;
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/* placeholder */
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};
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can0: can@e6e80000 {
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reg = <0 0xe6e80000 0 0x1000>;
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/* placeholder */
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};
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can1: can@e6e88000 {
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reg = <0 0xe6e88000 0 0x1000>;
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/* placeholder */
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};
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rcar_sound: sound@ec500000 {
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reg = <0 0xec500000 0 0x1000>;
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rcar_sound,dvc {
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dvc0: dvc-0 {};
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dvc1: dvc-1 {};
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};
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rcar_sound,src {
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src2: src-2 {};
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src3: src-3 {};
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};
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rcar_sound,ssi {
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ssi0: ssi-0 {};
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ssi1: ssi-1 {};
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};
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/* placeholder */
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};
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pci0: pci@ee090000 {
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reg = <0 0xee090000 0 0xc00>;
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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/* placeholder */
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};
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pci1: pci@ee0d0000 {
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reg = <0 0xee0d0000 0 0xc00>;
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bus-range = <1 1>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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/* placeholder */
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};
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sdhi1: sd@ee140000 {
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reg = <0 0xee140000 0 0x100>;
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/* placeholder */
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};
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sdhi2: sd@ee160000 {
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reg = <0 0xee160000 0 0x100>;
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/* placeholder */
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
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<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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du: display@feb00000 {
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reg = <0 0xfeb00000 0 0x40000>,
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<0 0xfeb90000 0 0x1c>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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du_out_rgb: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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du_out_lvds0: endpoint {
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};
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};
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};
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/* placeholder */
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};
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/* External USB clock - can be overridden by the board */
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usb_extal_clk: usb_extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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