Second set of FPGA Manager changes for 5.13-rc1
FPGA Manager: - Russ' first change improves port_enable reliability - Russ' second change adds a new device ID for a DFL device - Geert's change updates the examples in binding with dt overlay sugar syntax All patches have been reviewed on the mailing list, and have been in the last linux-next releases (as part of my for-next branch) without issues. Signed-off-by: Moritz Fischer <mdf@kernel.org> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRORt0E5Sb/c/mZMgkXxQAtim5VSwUCYG5feQAKCRAXxQAtim5V S1v3AQDR8dK1Bfoa8h8QHM+Xhb8UNkoC70Fbl/znQrTbRPimtAEAkgmKgElijBdL zE+zMFa0OUnkBCHW2IQZXfuu+qI9GQw= =P0ck -----END PGP SIGNATURE----- Merge tag 'fpga-late-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next Moritz writes: Second set of FPGA Manager changes for 5.13-rc1 FPGA Manager: - Russ' first change improves port_enable reliability - Russ' second change adds a new device ID for a DFL device - Geert's change updates the examples in binding with dt overlay sugar syntax All patches have been reviewed on the mailing list, and have been in the last linux-next releases (as part of my for-next branch) without issues. Signed-off-by: Moritz Fischer <mdf@kernel.org> * tag 'fpga-late-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: dfl: pci: add DID for D5005 PAC cards dt-bindings: fpga: fpga-region: Convert to sugar syntax fpga: dfl: afu: harden port enable logic fpga: Add support for Xilinx DFX AXI Shutdown manager dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown manager fpga: xilinx-pr-decoupler: Simplify code by using dev_err_probe() fpga: fpga-mgr: xilinx-spi: fix error messages on -EPROBE_DEFER
This commit is contained in:
Greg Kroah-Hartman
commit
d7ea31ca4d
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@ -245,36 +245,31 @@ Base tree contains:
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Overlay contains:
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/dts-v1/ /plugin/;
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/ {
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fragment@0 {
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target = <&fpga_region0>;
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#address-cells = <1>;
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#size-cells = <1>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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/dts-v1/;
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/plugin/;
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firmware-name = "soc_system.rbf";
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fpga-bridges = <&fpga_bridge1>;
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ranges = <0x20000 0xff200000 0x100000>,
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<0x0 0xc0000000 0x20000000>;
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&fpga_region0 {
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#address-cells = <1>;
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#size-cells = <1>;
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gpio@10040 {
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compatible = "altr,pio-1.0";
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reg = <0x10040 0x20>;
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altr,ngpio = <4>;
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#gpio-cells = <2>;
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clocks = <2>;
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gpio-controller;
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};
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firmware-name = "soc_system.rbf";
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fpga-bridges = <&fpga_bridge1>;
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ranges = <0x20000 0xff200000 0x100000>,
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<0x0 0xc0000000 0x20000000>;
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onchip-memory {
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device_type = "memory";
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compatible = "altr,onchipmem-15.1";
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reg = <0x0 0x10000>;
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};
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};
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gpio@10040 {
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compatible = "altr,pio-1.0";
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reg = <0x10040 0x20>;
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altr,ngpio = <4>;
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#gpio-cells = <2>;
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clocks = <2>;
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gpio-controller;
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};
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onchip-memory {
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device_type = "memory";
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compatible = "altr,onchipmem-15.1";
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reg = <0x0 0x10000>;
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};
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};
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@ -371,25 +366,22 @@ Live Device Tree contains:
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};
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DT Overlay contains:
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/dts-v1/ /plugin/;
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/ {
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fragment@0 {
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target = <&fpga_region0>;
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/dts-v1/;
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/plugin/;
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&fpga_region0 {
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#address-cells = <1>;
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#size-cells = <1>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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firmware-name = "zynq-gpio.bin";
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firmware-name = "zynq-gpio.bin";
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gpio1: gpio@40000000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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reg = <0x40000000 0x10000>;
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gpio-controller;
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#gpio-cells = <0x2>;
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xlnx,gpio-width= <0x6>;
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};
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gpio1: gpio@40000000 {
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compatible = "xlnx,xps-gpio-1.00.a";
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reg = <0x40000000 0x10000>;
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gpio-controller;
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#gpio-cells = <0x2>;
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xlnx,gpio-width= <0x6>;
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};
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};
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@ -402,41 +394,37 @@ This example programs the FPGA to have two regions that can later be partially
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configured. Each region has its own bridge in the FPGA fabric.
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DT Overlay contains:
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/dts-v1/ /plugin/;
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/ {
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fragment@0 {
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target = <&fpga_region0>;
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#address-cells = <1>;
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#size-cells = <1>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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firmware-name = "base.rbf";
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/dts-v1/;
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/plugin/;
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fpga-bridge@4400 {
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compatible = "altr,freeze-bridge-controller";
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reg = <0x4400 0x10>;
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&fpga_region0 {
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#address-cells = <1>;
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#size-cells = <1>;
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fpga_region1: fpga-region1 {
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compatible = "fpga-region";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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};
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};
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firmware-name = "base.rbf";
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fpga-bridge@4420 {
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compatible = "altr,freeze-bridge-controller";
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reg = <0x4420 0x10>;
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fpga-bridge@4400 {
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compatible = "altr,freeze-bridge-controller";
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reg = <0x4400 0x10>;
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fpga_region2: fpga-region2 {
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compatible = "fpga-region";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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};
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};
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fpga_region1: fpga-region1 {
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compatible = "fpga-region";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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};
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};
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fpga-bridge@4420 {
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compatible = "altr,freeze-bridge-controller";
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reg = <0x4420 0x10>;
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fpga_region2: fpga-region2 {
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compatible = "fpga-region";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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};
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};
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};
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@ -451,28 +439,23 @@ differences are that the FPGA is partially reconfigured due to the
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"partial-fpga-config" boolean and the only bridge that is controlled during
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programming is the FPGA based bridge of fpga_region1.
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/dts-v1/ /plugin/;
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/ {
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fragment@0 {
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target = <&fpga_region1>;
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#address-cells = <1>;
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#size-cells = <1>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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/dts-v1/;
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/plugin/;
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firmware-name = "soc_image2.rbf";
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partial-fpga-config;
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&fpga_region1 {
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#address-cells = <1>;
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#size-cells = <1>;
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gpio@10040 {
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compatible = "altr,pio-1.0";
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reg = <0x10040 0x20>;
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clocks = <0x2>;
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altr,ngpio = <0x4>;
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#gpio-cells = <0x2>;
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gpio-controller;
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};
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};
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firmware-name = "soc_image2.rbf";
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partial-fpga-config;
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gpio@10040 {
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compatible = "altr,pio-1.0";
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reg = <0x10040 0x20>;
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clocks = <0x2>;
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altr,ngpio = <0x4>;
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#gpio-cells = <0x2>;
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gpio-controller;
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};
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};
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@ -52,7 +52,7 @@ static int afu_port_err_clear(struct device *dev, u64 err)
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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struct platform_device *pdev = to_platform_device(dev);
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void __iomem *base_err, *base_hdr;
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int ret = -EBUSY;
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int enable_ret = 0, ret = -EBUSY;
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u64 v;
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base_err = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
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@ -96,18 +96,20 @@ static int afu_port_err_clear(struct device *dev, u64 err)
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v = readq(base_err + PORT_FIRST_ERROR);
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writeq(v, base_err + PORT_FIRST_ERROR);
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} else {
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dev_warn(dev, "%s: received 0x%llx, expected 0x%llx\n",
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__func__, v, err);
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ret = -EINVAL;
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}
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/* Clear mask */
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__afu_port_err_mask(dev, false);
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/* Enable the Port by clear the reset */
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__afu_port_enable(pdev);
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/* Enable the Port by clearing the reset */
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enable_ret = __afu_port_enable(pdev);
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done:
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mutex_unlock(&pdata->lock);
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return ret;
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return enable_ret ? enable_ret : ret;
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}
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static ssize_t errors_show(struct device *dev, struct device_attribute *attr,
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@ -21,6 +21,9 @@
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#include "dfl-afu.h"
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#define RST_POLL_INVL 10 /* us */
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#define RST_POLL_TIMEOUT 1000 /* us */
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/**
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* __afu_port_enable - enable a port by clear reset
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* @pdev: port platform device.
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@ -32,7 +35,7 @@
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*
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* The caller needs to hold lock for protection.
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*/
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void __afu_port_enable(struct platform_device *pdev)
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int __afu_port_enable(struct platform_device *pdev)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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void __iomem *base;
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@ -41,7 +44,7 @@ void __afu_port_enable(struct platform_device *pdev)
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WARN_ON(!pdata->disable_count);
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if (--pdata->disable_count != 0)
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return;
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return 0;
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base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
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@ -49,10 +52,20 @@ void __afu_port_enable(struct platform_device *pdev)
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v = readq(base + PORT_HDR_CTRL);
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v &= ~PORT_CTRL_SFTRST;
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writeq(v, base + PORT_HDR_CTRL);
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}
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#define RST_POLL_INVL 10 /* us */
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#define RST_POLL_TIMEOUT 1000 /* us */
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/*
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* HW clears the ack bit to indicate that the port is fully out
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* of reset.
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*/
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if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
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!(v & PORT_CTRL_SFTRST_ACK),
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RST_POLL_INVL, RST_POLL_TIMEOUT)) {
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dev_err(&pdev->dev, "timeout, failure to enable device\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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/**
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* __afu_port_disable - disable a port by hold reset
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@ -86,7 +99,7 @@ int __afu_port_disable(struct platform_device *pdev)
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if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
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v & PORT_CTRL_SFTRST_ACK,
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RST_POLL_INVL, RST_POLL_TIMEOUT)) {
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dev_err(&pdev->dev, "timeout, fail to reset device\n");
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dev_err(&pdev->dev, "timeout, failure to disable device\n");
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return -ETIMEDOUT;
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}
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@ -110,10 +123,10 @@ static int __port_reset(struct platform_device *pdev)
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int ret;
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ret = __afu_port_disable(pdev);
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if (!ret)
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__afu_port_enable(pdev);
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if (ret)
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return ret;
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return ret;
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return __afu_port_enable(pdev);
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}
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static int port_reset(struct platform_device *pdev)
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@ -872,11 +885,11 @@ static int afu_dev_destroy(struct platform_device *pdev)
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static int port_enable_set(struct platform_device *pdev, bool enable)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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int ret = 0;
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int ret;
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mutex_lock(&pdata->lock);
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if (enable)
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__afu_port_enable(pdev);
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ret = __afu_port_enable(pdev);
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else
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ret = __afu_port_disable(pdev);
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mutex_unlock(&pdata->lock);
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@ -80,7 +80,7 @@ struct dfl_afu {
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};
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/* hold pdata->lock when call __afu_port_enable/disable */
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void __afu_port_enable(struct platform_device *pdev);
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int __afu_port_enable(struct platform_device *pdev);
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int __afu_port_disable(struct platform_device *pdev);
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void afu_mmio_region_init(struct dfl_feature_platform_data *pdata);
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@ -69,14 +69,16 @@ static void cci_pci_free_irq(struct pci_dev *pcidev)
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}
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/* PCI Device ID */
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#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
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#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
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#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
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#define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
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#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
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#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
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#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
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#define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
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#define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B
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/* VF Device */
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#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
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#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
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#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
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#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
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#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
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#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
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#define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C
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static struct pci_device_id cci_pcie_id_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
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@ -86,6 +88,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
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{0,}
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};
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MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
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|
|
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|||
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