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anolis: perf/x86/uncore: Add L3 PMU support for Hygon family 18h model 6h 

ANBZ: #5455

Adjust the L3 PMU slicemask and threadmask for Hygon family 18h
model 6h processor.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Reviewed-by: Artie Ding <artie.ding@linux.alibaba.com>
Link: https://gitee.com/anolis/cloud-kernel/pulls/2536
Signed-off-by: Jinliang Zheng <alexjlzheng@tencent.com>
Reviewed-by: caelli <caelli@tencent.com>
Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
This commit is contained in:
Pu Wen 2023-12-21 20:41:03 +08:00 committed by Jianping Liu
parent e45c93c358
commit d7b445324e
2 changed files with 59 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
arch/x86/events/amd/uncore.c
View File

@ -186,10 +186,21 @@ static void amd_uncore_del(struct perf_event *event, int flags)
*/
static u64 l3_thread_slice_mask(u64 config)
{
if (boot_cpu_data.x86 <= 0x18)
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
boot_cpu_data.x86 <= 0x18)
return ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) |
((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK);
if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
boot_cpu_data.x86 == 0x18) {
if (boot_cpu_data.x86_model == 0x6)
return ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) |
((config & HYGON_L3_THREAD_MASK) ? : HYGON_L3_THREAD_MASK);
else
return ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) |
((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK);
}
/*
* If the user doesn't specify a threadmask, they're not trying to
* count core 0, so we enable all cores & threads.
@ -247,6 +258,13 @@ static int amd_uncore_event_init(struct perf_event *event)
return 0;
}
static umode_t
hygon_f18h_m6h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, int i)
{
return boot_cpu_data.x86 == 0x18 && boot_cpu_data.x86_model == 0x6 ?
attr->mode : 0;
}
static ssize_t amd_uncore_attr_show_cpumask(struct device *dev,
struct device_attribute *attr,
char *buf)
@ -296,6 +314,8 @@ DEFINE_UNCORE_FORMAT_ATTR(threadmask2, threadmask, "config:56-57"); /* F19h L
DEFINE_UNCORE_FORMAT_ATTR(enallslices, enallslices, "config:46"); /* F19h L3 */
DEFINE_UNCORE_FORMAT_ATTR(enallcores, enallcores, "config:47"); /* F19h L3 */
DEFINE_UNCORE_FORMAT_ATTR(sliceid, sliceid, "config:48-50"); /* F19h L3 */
DEFINE_UNCORE_FORMAT_ATTR(slicemask4, slicemask, "config:28-31"); /* F18h L3 */
DEFINE_UNCORE_FORMAT_ATTR(threadmask32, threadmask, "config:32-63"); /* F18h L3 */
static struct attribute *amd_uncore_df_format_attr[] = {
&format_attr_event12.attr, /* event14 if F17h+ */
@ -314,6 +334,12 @@ static struct attribute *amd_uncore_l3_format_attr[] = {
NULL,
};
/* F18h M06h unique L3 attributes */
static struct attribute *hygon_f18h_m6h_uncore_l3_format_attr[] = {
&format_attr_slicemask4.attr, /* slicemask */
NULL,
};
static struct attribute_group amd_uncore_df_format_group = {
.name = "format",
.attrs = amd_uncore_df_format_attr,
@ -324,6 +350,12 @@ static struct attribute_group amd_uncore_l3_format_group = {
.attrs = amd_uncore_l3_format_attr,
};
static struct attribute_group hygon_f18h_m6h_uncore_l3_format_group = {
.name = "format",
.attrs = hygon_f18h_m6h_uncore_l3_format_attr,
.is_visible = hygon_f18h_m6h_uncore_is_visible,
};
static const struct attribute_group *amd_uncore_df_attr_groups[] = {
&amd_uncore_attr_group,
&amd_uncore_df_format_group,
@ -336,6 +368,11 @@ static const struct attribute_group *amd_uncore_l3_attr_groups[] = {
NULL,
};
static const struct attribute_group *hygon_uncore_l3_attr_update[] = {
&hygon_f18h_m6h_uncore_l3_format_group,
NULL,
};
static struct pmu amd_nb_pmu = {
.task_ctx_nr = perf_invalid_context,
.attr_groups = amd_uncore_df_attr_groups,
@ -610,11 +647,23 @@ static int __init amd_uncore_init(void)
*l3_attr++ = &format_attr_enallcores.attr;
*l3_attr++ = &format_attr_sliceid.attr;
*l3_attr++ = &format_attr_threadmask2.attr;
} else if (boot_cpu_data.x86 >= 0x17) {
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
boot_cpu_data.x86 >= 0x17) {
*l3_attr++ = &format_attr_event8.attr;
*l3_attr++ = &format_attr_umask.attr;
*l3_attr++ = &format_attr_slicemask.attr;
*l3_attr++ = &format_attr_threadmask8.attr;
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
boot_cpu_data.x86 == 0x18) {
*l3_attr++ = &format_attr_event8.attr;
*l3_attr++ = &format_attr_umask.attr;
*l3_attr++ = &format_attr_slicemask.attr;
if (boot_cpu_data.x86_model == 0x6) {
*l3_attr++ = &format_attr_threadmask32.attr;
amd_llc_pmu.attr_update = hygon_uncore_l3_attr_update;
} else {
*l3_attr++ = &format_attr_threadmask8.attr;
}
}
amd_uncore_llc = alloc_percpu(struct amd_uncore *);

8
arch/x86/include/asm/perf_event.h
View File

@ -48,6 +48,14 @@
#define INTEL_ARCH_EVENT_MASK \
(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
#define HYGON_L3_SLICE_SHIFT 28
#define HYGON_L3_SLICE_MASK \
(0xFULL << HYGON_L3_SLICE_SHIFT)
#define HYGON_L3_THREAD_SHIFT 32
#define HYGON_L3_THREAD_MASK \
(0xFFFFFFFFULL << HYGON_L3_THREAD_SHIFT)
#define AMD64_L3_SLICE_SHIFT 48
#define AMD64_L3_SLICE_MASK \
(0xFULL << AMD64_L3_SLICE_SHIFT)