drm/i915/pmu: Only use exclusive mmio access for gen7
On gen7, we have to avoid concurrent access to the same mmio cacheline, and so coordinate all mmio access with the uncore->lock. However, for pmu, we want to avoid perturbing the system and disabling interrupts unnecessarily, so restrict the w/a to gen7 where it is requied to prevent machine hangs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191108103511.20951-2-chris@chris-wilson.co.uk
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@ -292,6 +292,16 @@ add_sample(struct i915_pmu_sample *sample, u32 val)
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sample->cur += val;
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}
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static bool exclusive_mmio_access(const struct drm_i915_private *i915)
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{
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/*
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* We have to avoid concurrent mmio cache line access on gen7 or
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* risk a machine hang. For a fun history lesson dig out the old
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* userspace intel_gpu_top and run it on Ivybridge or Haswell!
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*/
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return IS_GEN(i915, 7);
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}
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static void
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engines_sample(struct intel_gt *gt, unsigned int period_ns)
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{
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@ -304,6 +314,7 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
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for_each_engine(engine, gt, id) {
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struct intel_engine_pmu *pmu = &engine->pmu;
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spinlock_t *mmio_lock;
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unsigned long flags;
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bool busy;
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u32 val;
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@ -311,7 +322,12 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
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if (!intel_engine_pm_get_if_awake(engine))
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continue;
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spin_lock_irqsave(&engine->uncore->lock, flags);
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mmio_lock = NULL;
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if (exclusive_mmio_access(i915))
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mmio_lock = &engine->uncore->lock;
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if (unlikely(mmio_lock))
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spin_lock_irqsave(mmio_lock, flags);
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val = ENGINE_READ_FW(engine, RING_CTL);
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if (val == 0) /* powerwell off => engine idle */
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@ -342,7 +358,8 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
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add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
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skip:
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spin_unlock_irqrestore(&engine->uncore->lock, flags);
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if (unlikely(mmio_lock))
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spin_unlock_irqrestore(mmio_lock, flags);
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intel_engine_pm_put(engine);
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}
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}
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