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mlxsw: Support FLOW_ACTION_MANGLE for SIP and DIP IPv4 addresses 

Spectrum-2 supports an ACL action SIP_DIP, which allows IPv4 and IPv6
source and destination addresses change. Offload suitable mangles to
the IPv4 address change action.

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Danielle Ratson 2022-02-06 17:36:11 +02:00 committed by David S. Miller
parent e3541022e4
commit d7809b620f
3 changed files with 47 additions and 0 deletions
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32
drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_actions.c
View File

@ -2002,6 +2002,38 @@ MLXSW_ITEM32(afa, ip, ip_63_32, 0x08, 0, 32);
*/
MLXSW_ITEM32(afa, ip, ip_31_0, 0x0C, 0, 32);
static void mlxsw_afa_ip_pack(char *payload, enum mlxsw_afa_ip_s_d s_d,
enum mlxsw_afa_ip_m_l m_l, u32 ip_31_0,
u32 ip_63_32)
{
mlxsw_afa_ip_s_d_set(payload, s_d);
mlxsw_afa_ip_m_l_set(payload, m_l);
mlxsw_afa_ip_ip_31_0_set(payload, ip_31_0);
mlxsw_afa_ip_ip_63_32_set(payload, ip_63_32);
}
int mlxsw_afa_block_append_ip(struct mlxsw_afa_block *block, bool is_dip,
bool is_lsb, u32 val_31_0, u32 val_63_32,
struct netlink_ext_ack *extack)
{
enum mlxsw_afa_ip_s_d s_d = is_dip ? MLXSW_AFA_IP_S_D_DIP :
MLXSW_AFA_IP_S_D_SIP;
enum mlxsw_afa_ip_m_l m_l = is_lsb ? MLXSW_AFA_IP_M_L_LSB :
MLXSW_AFA_IP_M_L_MSB;
char *act = mlxsw_afa_block_append_action(block,
MLXSW_AFA_IP_CODE,
MLXSW_AFA_IP_SIZE);
if (IS_ERR(act)) {
NL_SET_ERR_MSG_MOD(extack, "Cannot append IP action");
return PTR_ERR(act);
}
mlxsw_afa_ip_pack(act, s_d, m_l, val_31_0, val_63_32);
return 0;
}
EXPORT_SYMBOL(mlxsw_afa_block_append_ip);
/* L4 Port Action
* --------------
* The L4_PORT_ACTION is used for modifying the sport and dport fields of the packet, e.g. for NAT.

3
drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_actions.h
View File

@ -92,6 +92,9 @@ int mlxsw_afa_block_append_fid_set(struct mlxsw_afa_block *block, u16 fid,
int mlxsw_afa_block_append_mcrouter(struct mlxsw_afa_block *block,
u16 expected_irif, u16 min_mtu,
bool rmid_valid, u32 kvdl_index);
int mlxsw_afa_block_append_ip(struct mlxsw_afa_block *block, bool is_dip,
bool is_lsb, u32 val_31_0, u32 val_63_32,
struct netlink_ext_ack *extack);
int mlxsw_afa_block_append_l4port(struct mlxsw_afa_block *block, bool is_dport, u16 l4_port,
struct netlink_ext_ack *extack);
int mlxsw_afa_block_append_police(struct mlxsw_afa_block *block,

12
drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c
View File

@ -511,6 +511,8 @@ enum mlxsw_sp_acl_mangle_field {
MLXSW_SP_ACL_MANGLE_FIELD_IP_ECN,
MLXSW_SP_ACL_MANGLE_FIELD_IP_SPORT,
MLXSW_SP_ACL_MANGLE_FIELD_IP_DPORT,
MLXSW_SP_ACL_MANGLE_FIELD_IP4_SIP,
MLXSW_SP_ACL_MANGLE_FIELD_IP4_DIP,
};
struct mlxsw_sp_acl_mangle_action {
@ -561,6 +563,9 @@ static struct mlxsw_sp_acl_mangle_action mlxsw_sp_acl_mangle_actions[] = {
MLXSW_SP_ACL_MANGLE_ACTION_UDP(0, 0x0000ffff, 16, IP_SPORT),
MLXSW_SP_ACL_MANGLE_ACTION_UDP(0, 0xffff0000, 0, IP_DPORT),
MLXSW_SP_ACL_MANGLE_ACTION_IP4(12, 0x00000000, 0, IP4_SIP),
MLXSW_SP_ACL_MANGLE_ACTION_IP4(16, 0x00000000, 0, IP4_DIP),
};
static int
@ -615,6 +620,13 @@ static int mlxsw_sp2_acl_rulei_act_mangle_field(struct mlxsw_sp *mlxsw_sp,
return mlxsw_afa_block_append_l4port(rulei->act_block, false, val, extack);
case MLXSW_SP_ACL_MANGLE_FIELD_IP_DPORT:
return mlxsw_afa_block_append_l4port(rulei->act_block, true, val, extack);
/* IPv4 fields */
case MLXSW_SP_ACL_MANGLE_FIELD_IP4_SIP:
return mlxsw_afa_block_append_ip(rulei->act_block, false,
true, val, 0, extack);
case MLXSW_SP_ACL_MANGLE_FIELD_IP4_DIP:
return mlxsw_afa_block_append_ip(rulei->act_block, true,
true, val, 0, extack);
default:
break;
}