spi: dw-mid: convert to use dw_dmac instead of intel_mid_dma
intel_mid_dma seems to be unmaintained for a long time. Moreover, the IP block of DMA itself is the same in both dw_dmac and intel_mid_dma. This patch moves spi-dw-midpci to use dw_dmac driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -632,7 +632,7 @@ config SPI_DW_PCI
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config SPI_DW_MID_DMA
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bool "DMA support for DW SPI controller on Intel MID platform"
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depends on SPI_DW_PCI && INTEL_MID_DMAC
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depends on SPI_DW_PCI && DW_DMAC_PCI
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config SPI_DW_MMIO
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tristate "Memory-mapped io interface driver for DW SPI core"
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@ -23,29 +23,31 @@
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#include "spi-dw.h"
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#ifdef CONFIG_SPI_DW_MID_DMA
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#include <linux/intel_mid_dma.h>
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#include <linux/pci.h>
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#include <linux/platform_data/dma-dw.h>
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#define RX_BUSY 0
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#define TX_BUSY 1
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struct mid_dma {
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struct intel_mid_dma_slave dmas_tx;
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struct intel_mid_dma_slave dmas_rx;
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};
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static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
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static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
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static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
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{
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struct dw_spi *dws = param;
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struct dw_dma_slave *s = param;
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return dws->dma_dev == chan->device->dev;
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if (s->dma_dev != chan->device->dev)
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return false;
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chan->private = s;
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return true;
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}
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static int mid_spi_dma_init(struct dw_spi *dws)
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{
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struct mid_dma *dw_dma = dws->dma_priv;
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struct pci_dev *dma_dev;
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struct intel_mid_dma_slave *rxs, *txs;
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struct dw_dma_slave *tx = dws->dma_tx;
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struct dw_dma_slave *rx = dws->dma_rx;
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dma_cap_mask_t mask;
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/*
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@ -56,29 +58,21 @@ static int mid_spi_dma_init(struct dw_spi *dws)
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if (!dma_dev)
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return -ENODEV;
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dws->dma_dev = &dma_dev->dev;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/* 1. Init rx channel */
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dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
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rx->dma_dev = &dma_dev->dev;
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dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
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if (!dws->rxchan)
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goto err_exit;
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rxs = &dw_dma->dmas_rx;
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rxs->hs_mode = LNW_DMA_HW_HS;
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rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
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dws->rxchan->private = rxs;
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dws->master->dma_rx = dws->rxchan;
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/* 2. Init tx channel */
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dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
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tx->dma_dev = &dma_dev->dev;
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dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
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if (!dws->txchan)
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goto free_rxchan;
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txs = &dw_dma->dmas_tx;
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txs->hs_mode = LNW_DMA_HW_HS;
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txs->cfg_mode = LNW_DMA_MEM_TO_PER;
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dws->txchan->private = txs;
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dws->master->dma_tx = dws->txchan;
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dws->dma_inited = 1;
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@ -163,7 +157,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
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txconf.direction = DMA_MEM_TO_DEV;
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_maxburst = LNW_DMA_MSIZE_16;
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txconf.dst_maxburst = 16;
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txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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txconf.dst_addr_width = convert_dma_width(dws->dma_width);
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txconf.device_fc = false;
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@ -209,7 +203,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
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rxconf.direction = DMA_DEV_TO_MEM;
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_maxburst = LNW_DMA_MSIZE_16;
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rxconf.src_maxburst = 16;
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rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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rxconf.src_addr_width = convert_dma_width(dws->dma_width);
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rxconf.device_fc = false;
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@ -328,9 +322,8 @@ int dw_spi_mid_init(struct dw_spi *dws)
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iounmap(clk_reg);
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#ifdef CONFIG_SPI_DW_MID_DMA
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dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
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if (!dws->dma_priv)
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return -ENOMEM;
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dws->dma_tx = &mid_dma_tx;
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dws->dma_rx = &mid_dma_rx;
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dws->dma_ops = &mid_dma_ops;
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#endif
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return 0;
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@ -128,10 +128,10 @@ struct dw_spi {
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struct dma_chan *txchan;
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struct dma_chan *rxchan;
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unsigned long dma_chan_busy;
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struct device *dma_dev;
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dma_addr_t dma_addr; /* phy address of the Data register */
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struct dw_spi_dma_ops *dma_ops;
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void *dma_priv; /* platform relate info */
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void *dma_tx;
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void *dma_rx;
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/* Bus interface info */
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void *priv;
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