ipr: convert to generic DMA API
Even though the ipr driver is only used on PCI, convert it to use the generic DMA API. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Brian King <brking@linux.vnet.ibm.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
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6932fc677e
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d73341bff0
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@ -3942,8 +3942,9 @@ static int ipr_update_ioa_ucode(struct ipr_ioa_cfg *ioa_cfg,
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return -EIO;
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}
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sglist->num_dma_sg = pci_map_sg(ioa_cfg->pdev, sglist->scatterlist,
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sglist->num_sg, DMA_TO_DEVICE);
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sglist->num_dma_sg = dma_map_sg(&ioa_cfg->pdev->dev,
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sglist->scatterlist, sglist->num_sg,
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DMA_TO_DEVICE);
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if (!sglist->num_dma_sg) {
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spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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@ -5571,7 +5572,7 @@ static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg,
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nseg = scsi_dma_map(scsi_cmd);
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if (nseg < 0) {
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if (printk_ratelimit())
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dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
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dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
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return -1;
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}
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@ -5622,7 +5623,7 @@ static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg,
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nseg = scsi_dma_map(scsi_cmd);
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if (nseg < 0) {
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dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
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dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
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return -1;
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}
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@ -8392,7 +8393,7 @@ static int ipr_reset_ucode_download_done(struct ipr_cmnd *ipr_cmd)
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struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
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struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
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pci_unmap_sg(ioa_cfg->pdev, sglist->scatterlist,
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dma_unmap_sg(&ioa_cfg->pdev->dev, sglist->scatterlist,
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sglist->num_sg, DMA_TO_DEVICE);
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ipr_cmd->job_step = ipr_reset_alert;
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@ -8832,7 +8833,7 @@ static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
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for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
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if (ioa_cfg->ipr_cmnd_list[i])
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pci_pool_free(ioa_cfg->ipr_cmd_pool,
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dma_pool_free(ioa_cfg->ipr_cmd_pool,
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ioa_cfg->ipr_cmnd_list[i],
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ioa_cfg->ipr_cmnd_list_dma[i]);
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@ -8840,7 +8841,7 @@ static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
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}
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if (ioa_cfg->ipr_cmd_pool)
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pci_pool_destroy(ioa_cfg->ipr_cmd_pool);
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dma_pool_destroy(ioa_cfg->ipr_cmd_pool);
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kfree(ioa_cfg->ipr_cmnd_list);
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kfree(ioa_cfg->ipr_cmnd_list_dma);
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@ -8861,25 +8862,24 @@ static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
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int i;
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kfree(ioa_cfg->res_entries);
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pci_free_consistent(ioa_cfg->pdev, sizeof(struct ipr_misc_cbs),
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ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
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dma_free_coherent(&ioa_cfg->pdev->dev, sizeof(struct ipr_misc_cbs),
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ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
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ipr_free_cmd_blks(ioa_cfg);
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for (i = 0; i < ioa_cfg->hrrq_num; i++)
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pci_free_consistent(ioa_cfg->pdev,
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sizeof(u32) * ioa_cfg->hrrq[i].size,
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ioa_cfg->hrrq[i].host_rrq,
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ioa_cfg->hrrq[i].host_rrq_dma);
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dma_free_coherent(&ioa_cfg->pdev->dev,
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sizeof(u32) * ioa_cfg->hrrq[i].size,
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ioa_cfg->hrrq[i].host_rrq,
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ioa_cfg->hrrq[i].host_rrq_dma);
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pci_free_consistent(ioa_cfg->pdev, ioa_cfg->cfg_table_size,
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ioa_cfg->u.cfg_table,
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ioa_cfg->cfg_table_dma);
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dma_free_coherent(&ioa_cfg->pdev->dev, ioa_cfg->cfg_table_size,
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ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
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for (i = 0; i < IPR_NUM_HCAMS; i++) {
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pci_free_consistent(ioa_cfg->pdev,
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sizeof(struct ipr_hostrcb),
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ioa_cfg->hostrcb[i],
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ioa_cfg->hostrcb_dma[i]);
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dma_free_coherent(&ioa_cfg->pdev->dev,
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sizeof(struct ipr_hostrcb),
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ioa_cfg->hostrcb[i],
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ioa_cfg->hostrcb_dma[i]);
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}
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ipr_free_dump(ioa_cfg);
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@ -8940,7 +8940,7 @@ static int ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
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dma_addr_t dma_addr;
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int i, entries_each_hrrq, hrrq_id = 0;
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ioa_cfg->ipr_cmd_pool = pci_pool_create(IPR_NAME, ioa_cfg->pdev,
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ioa_cfg->ipr_cmd_pool = dma_pool_create(IPR_NAME, &ioa_cfg->pdev->dev,
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sizeof(struct ipr_cmnd), 512, 0);
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if (!ioa_cfg->ipr_cmd_pool)
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@ -8990,7 +8990,7 @@ static int ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
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}
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for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
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ipr_cmd = pci_pool_alloc(ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr);
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ipr_cmd = dma_pool_alloc(ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr);
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if (!ipr_cmd) {
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ipr_free_cmd_blks(ioa_cfg);
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@ -9061,9 +9061,10 @@ static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
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ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg;
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}
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ioa_cfg->vpd_cbs = pci_alloc_consistent(ioa_cfg->pdev,
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sizeof(struct ipr_misc_cbs),
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&ioa_cfg->vpd_cbs_dma);
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ioa_cfg->vpd_cbs = dma_alloc_coherent(&pdev->dev,
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sizeof(struct ipr_misc_cbs),
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&ioa_cfg->vpd_cbs_dma,
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GFP_KERNEL);
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if (!ioa_cfg->vpd_cbs)
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goto out_free_res_entries;
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@ -9072,13 +9073,14 @@ static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
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goto out_free_vpd_cbs;
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for (i = 0; i < ioa_cfg->hrrq_num; i++) {
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ioa_cfg->hrrq[i].host_rrq = pci_alloc_consistent(ioa_cfg->pdev,
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ioa_cfg->hrrq[i].host_rrq = dma_alloc_coherent(&pdev->dev,
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sizeof(u32) * ioa_cfg->hrrq[i].size,
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&ioa_cfg->hrrq[i].host_rrq_dma);
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&ioa_cfg->hrrq[i].host_rrq_dma,
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GFP_KERNEL);
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if (!ioa_cfg->hrrq[i].host_rrq) {
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while (--i > 0)
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pci_free_consistent(pdev,
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dma_free_coherent(&pdev->dev,
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sizeof(u32) * ioa_cfg->hrrq[i].size,
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ioa_cfg->hrrq[i].host_rrq,
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ioa_cfg->hrrq[i].host_rrq_dma);
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@ -9087,17 +9089,19 @@ static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
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ioa_cfg->hrrq[i].ioa_cfg = ioa_cfg;
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}
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ioa_cfg->u.cfg_table = pci_alloc_consistent(ioa_cfg->pdev,
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ioa_cfg->cfg_table_size,
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&ioa_cfg->cfg_table_dma);
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ioa_cfg->u.cfg_table = dma_alloc_coherent(&pdev->dev,
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ioa_cfg->cfg_table_size,
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&ioa_cfg->cfg_table_dma,
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GFP_KERNEL);
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if (!ioa_cfg->u.cfg_table)
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goto out_free_host_rrq;
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for (i = 0; i < IPR_NUM_HCAMS; i++) {
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ioa_cfg->hostrcb[i] = pci_alloc_consistent(ioa_cfg->pdev,
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sizeof(struct ipr_hostrcb),
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&ioa_cfg->hostrcb_dma[i]);
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ioa_cfg->hostrcb[i] = dma_alloc_coherent(&pdev->dev,
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sizeof(struct ipr_hostrcb),
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&ioa_cfg->hostrcb_dma[i],
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GFP_KERNEL);
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if (!ioa_cfg->hostrcb[i])
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goto out_free_hostrcb_dma;
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@ -9121,25 +9125,24 @@ out:
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out_free_hostrcb_dma:
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while (i-- > 0) {
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pci_free_consistent(pdev, sizeof(struct ipr_hostrcb),
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ioa_cfg->hostrcb[i],
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ioa_cfg->hostrcb_dma[i]);
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dma_free_coherent(&pdev->dev, sizeof(struct ipr_hostrcb),
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ioa_cfg->hostrcb[i],
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ioa_cfg->hostrcb_dma[i]);
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}
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pci_free_consistent(pdev, ioa_cfg->cfg_table_size,
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ioa_cfg->u.cfg_table,
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ioa_cfg->cfg_table_dma);
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dma_free_coherent(&pdev->dev, ioa_cfg->cfg_table_size,
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ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
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out_free_host_rrq:
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for (i = 0; i < ioa_cfg->hrrq_num; i++) {
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pci_free_consistent(pdev,
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sizeof(u32) * ioa_cfg->hrrq[i].size,
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ioa_cfg->hrrq[i].host_rrq,
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ioa_cfg->hrrq[i].host_rrq_dma);
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dma_free_coherent(&pdev->dev,
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sizeof(u32) * ioa_cfg->hrrq[i].size,
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ioa_cfg->hrrq[i].host_rrq,
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ioa_cfg->hrrq[i].host_rrq_dma);
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}
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out_ipr_free_cmd_blocks:
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ipr_free_cmd_blks(ioa_cfg);
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out_free_vpd_cbs:
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pci_free_consistent(pdev, sizeof(struct ipr_misc_cbs),
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ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
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dma_free_coherent(&pdev->dev, sizeof(struct ipr_misc_cbs),
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ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
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out_free_res_entries:
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kfree(ioa_cfg->res_entries);
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goto out;
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@ -9579,13 +9582,13 @@ static int ipr_probe_ioa(struct pci_dev *pdev,
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ipr_init_regs(ioa_cfg);
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if (ioa_cfg->sis64) {
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
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rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
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if (rc < 0) {
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dev_dbg(&pdev->dev, "Failed to set 64 bit PCI DMA mask\n");
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
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}
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} else
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
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if (rc < 0) {
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dev_err(&pdev->dev, "Failed to set PCI DMA mask\n");
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@ -1549,7 +1549,7 @@ struct ipr_ioa_cfg {
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struct ipr_misc_cbs *vpd_cbs;
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dma_addr_t vpd_cbs_dma;
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struct pci_pool *ipr_cmd_pool;
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struct dma_pool *ipr_cmd_pool;
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struct ipr_cmnd *reset_cmd;
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int (*reset) (struct ipr_cmnd *);
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