drm/i915/icl: Combine all port/combophy macros at one place
This patch combines CNL/ICL specific port/combophy macros together at one location. This is prework for patches later in series where new macros to find port/combophy register will be introduced. v2: remove wrong empty line Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181012234717.8284-1-lucas.demarchi@intel.com
This commit is contained in:
Mahesh Kumar
Rodrigo Vivi
parent
a54270d3a9
commit
d72e84ccba
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@ -1631,14 +1631,41 @@ enum i915_power_well_id {
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#define PHY_RESERVED (1 << 7)
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#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
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#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
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#define CL_POWER_DOWN_ENABLE (1 << 4)
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#define SUS_CLOCK_CONFIG (3 << 0)
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#define _PORT_CL1CM_DW9_A 0x162024
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#define _PORT_CL1CM_DW9_BC 0x6C024
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#define IREF0RC_OFFSET_SHIFT 8
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#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
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#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
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#define _PORT_CL1CM_DW10_A 0x162028
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#define _PORT_CL1CM_DW10_BC 0x6C028
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#define IREF1RC_OFFSET_SHIFT 8
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#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
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#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
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#define _PORT_CL1CM_DW28_A 0x162070
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#define _PORT_CL1CM_DW28_BC 0x6C070
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#define OCL1_POWER_DOWN_EN (1 << 23)
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#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
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#define SUS_CLK_CONFIG 0x3
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#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
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#define _PORT_CL1CM_DW30_A 0x162078
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#define _PORT_CL1CM_DW30_BC 0x6C078
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#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
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#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
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/*
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* CNL/ICL Port/COMBO-PHY Registers
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*/
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/* CNL/ICL Port CL_DW registers */
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#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
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#define _ICL_PORT_CL_DW5_A 0x162014
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#define _ICL_PORT_CL_DW5_B 0x6C014
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#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
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_ICL_PORT_CL_DW5_B)
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#define CL_POWER_DOWN_ENABLE (1 << 4)
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#define SUS_CLOCK_CONFIG (3 << 0)
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#define _CNL_PORT_CL_DW10_A 0x162028
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#define _ICL_PORT_CL_DW10_B 0x6c028
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@ -1660,18 +1687,6 @@ enum i915_power_well_id {
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#define PWR_DOWN_LN_MASK (0xf << 4)
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#define PWR_DOWN_LN_SHIFT 4
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#define _PORT_CL1CM_DW9_A 0x162024
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#define _PORT_CL1CM_DW9_BC 0x6C024
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#define IREF0RC_OFFSET_SHIFT 8
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#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
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#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
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#define _PORT_CL1CM_DW10_A 0x162028
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#define _PORT_CL1CM_DW10_BC 0x6C028
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#define IREF1RC_OFFSET_SHIFT 8
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#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
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#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
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#define _ICL_PORT_CL_DW12_A 0x162030
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#define _ICL_PORT_CL_DW12_B 0x6C030
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#define ICL_LANE_ENABLE_AUX (1 << 0)
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@ -1679,18 +1694,49 @@ enum i915_power_well_id {
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_ICL_PORT_CL_DW12_A, \
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_ICL_PORT_CL_DW12_B)
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#define _PORT_CL1CM_DW28_A 0x162070
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#define _PORT_CL1CM_DW28_BC 0x6C070
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#define OCL1_POWER_DOWN_EN (1 << 23)
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#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
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#define SUS_CLK_CONFIG 0x3
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#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
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/* CNL/ICL Port COMP_DW registers */
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#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
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#define _ICL_PORT_COMP_DW0_A 0x162100
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#define _ICL_PORT_COMP_DW0_B 0x6C100
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#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
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_ICL_PORT_COMP_DW0_B)
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#define COMP_INIT (1 << 31)
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#define _PORT_CL1CM_DW30_A 0x162078
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#define _PORT_CL1CM_DW30_BC 0x6C078
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#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
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#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
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#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
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#define _ICL_PORT_COMP_DW1_A 0x162104
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#define _ICL_PORT_COMP_DW1_B 0x6C104
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#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
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_ICL_PORT_COMP_DW1_B)
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#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
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#define _ICL_PORT_COMP_DW3_A 0x16210C
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#define _ICL_PORT_COMP_DW3_B 0x6C10C
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#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
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_ICL_PORT_COMP_DW3_B)
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#define PROCESS_INFO_DOT_0 (0 << 26)
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#define PROCESS_INFO_DOT_1 (1 << 26)
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#define PROCESS_INFO_DOT_4 (2 << 26)
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#define PROCESS_INFO_MASK (7 << 26)
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#define PROCESS_INFO_SHIFT 26
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#define VOLTAGE_INFO_0_85V (0 << 24)
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#define VOLTAGE_INFO_0_95V (1 << 24)
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#define VOLTAGE_INFO_1_05V (2 << 24)
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#define VOLTAGE_INFO_MASK (3 << 24)
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#define VOLTAGE_INFO_SHIFT 24
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#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
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#define _ICL_PORT_COMP_DW9_A 0x162124
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#define _ICL_PORT_COMP_DW9_B 0x6C124
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#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
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_ICL_PORT_COMP_DW9_B)
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#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
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#define _ICL_PORT_COMP_DW10_A 0x162128
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#define _ICL_PORT_COMP_DW10_B 0x6C128
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#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
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_ICL_PORT_COMP_DW10_A, \
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_ICL_PORT_COMP_DW10_B)
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/* CNL/ICL Port PCS registers */
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#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
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#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
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#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
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@ -1734,7 +1780,7 @@ enum i915_power_well_id {
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_ICL_PORT_PCS_DW1_AUX_B)
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#define COMMON_KEEPER_EN (1 << 26)
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/* CNL Port TX registers */
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/* CNL/ICL Port TX registers */
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#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
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#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
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#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
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@ -2054,45 +2100,6 @@ enum i915_power_well_id {
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#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
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#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
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#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
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#define COMP_INIT (1 << 31)
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#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
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#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
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#define PROCESS_INFO_DOT_0 (0 << 26)
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#define PROCESS_INFO_DOT_1 (1 << 26)
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#define PROCESS_INFO_DOT_4 (2 << 26)
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#define PROCESS_INFO_MASK (7 << 26)
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#define PROCESS_INFO_SHIFT 26
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#define VOLTAGE_INFO_0_85V (0 << 24)
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#define VOLTAGE_INFO_0_95V (1 << 24)
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#define VOLTAGE_INFO_1_05V (2 << 24)
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#define VOLTAGE_INFO_MASK (3 << 24)
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#define VOLTAGE_INFO_SHIFT 24
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#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
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#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
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#define _ICL_PORT_COMP_DW0_A 0x162100
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#define _ICL_PORT_COMP_DW0_B 0x6C100
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#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
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_ICL_PORT_COMP_DW0_B)
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#define _ICL_PORT_COMP_DW1_A 0x162104
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#define _ICL_PORT_COMP_DW1_B 0x6C104
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#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
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_ICL_PORT_COMP_DW1_B)
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#define _ICL_PORT_COMP_DW3_A 0x16210C
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#define _ICL_PORT_COMP_DW3_B 0x6C10C
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#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
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_ICL_PORT_COMP_DW3_B)
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#define _ICL_PORT_COMP_DW9_A 0x162124
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#define _ICL_PORT_COMP_DW9_B 0x6C124
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#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
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_ICL_PORT_COMP_DW9_B)
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#define _ICL_PORT_COMP_DW10_A 0x162128
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#define _ICL_PORT_COMP_DW10_B 0x6C128
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#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
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_ICL_PORT_COMP_DW10_A, \
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_ICL_PORT_COMP_DW10_B)
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/* ICL PHY DFLEX registers */
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#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
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#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
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