arm: dts: add Nuvoton NPCM750 device tree
Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Brendan Higgins
Arnd Bergmann
parent
1796483fcd
commit
d6bdd009c2
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@ -0,0 +1,42 @@
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=========================================================
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Secondary CPU enable-method "nuvoton,npcm750-smp" binding
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=========================================================
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To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
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defined in the "cpus" node.
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Enable method name: "nuvoton,npcm750-smp"
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Compatible machines: "nuvoton,npcm750"
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Compatible CPUs: "arm,cortex-a9"
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Related properties: (none)
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Note:
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This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
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"nuvoton,npcm750-gcr".
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "nuvoton,npcm750-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk NPCM7XX_CLK_CPU>;
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clock-names = "clk_cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk NPCM7XX_CLK_CPU>;
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clock-names = "clk_cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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@ -0,0 +1,6 @@
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NPCM Platforms Device Tree Bindings
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-----------------------------------
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NPCM750 SoC
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Required root node properties:
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- compatible = "nuvoton,npcm750";
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@ -304,6 +304,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \
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dtb-$(CONFIG_ARCH_LPC32XX) += \
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lpc3250-ea3250.dtb \
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lpc3250-phy3250.dtb
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dtb-$(CONFIG_ARCH_NPCM750) += \
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nuvoton-npcm750-evb.dtb
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dtb-$(CONFIG_MACH_MESON6) += \
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meson6-atv1200.dtb
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dtb-$(CONFIG_MACH_MESON8) += \
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@ -0,0 +1,35 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology corporation.
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// Copyright 2018 Google, Inc.
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/dts-v1/;
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#include "nuvoton-npcm750.dtsi"
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/ {
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model = "Nuvoton npcm750 Development Board (Device Tree)";
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compatible = "nuvoton,npcm750";
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chosen {
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stdout-path = &serial3;
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};
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memory {
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reg = <0 0x40000000>;
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};
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};
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&serial0 {
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status = "okay";
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};
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&serial1 {
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status = "okay";
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};
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&serial2 {
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status = "okay";
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};
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&serial3 {
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status = "okay";
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};
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@ -0,0 +1,165 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology corporation.
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// Copyright 2018 Google, Inc.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "nuvoton,npcm750-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk 10>;
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clock-names = "clk_cpu";
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reg = <0>;
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next-level-cache = <&l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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clocks = <&clk 10>;
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clock-names = "clk_cpu";
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reg = <1>;
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next-level-cache = <&l2>;
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};
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};
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/* external clock signal rg1refck, supplied by the phy */
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clk-rg1refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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/* external clock signal rg2refck, supplied by the phy */
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clk-rg2refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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clk-xin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0xf0000000 0x00900000>;
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gcr: gcr@800000 {
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compatible = "nuvoton,npcm750-gcr", "syscon",
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"simple-mfd";
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reg = <0x800000 0x1000>;
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};
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scu: scu@3fe000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x3fe000 0x1000>;
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};
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l2: cache-controller@3fc000 {
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compatible = "arm,pl310-cache";
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reg = <0x3fc000 0x1000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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clocks = <&clk 22>;
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arm,shared-override;
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};
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gic: interrupt-controller@3ff000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x3ff000 0x1000>,
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<0x3fe100 0x100>;
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};
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timer@3fe600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x3fe600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&clk 15>;
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};
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};
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm750-clk";
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#clock-cells = <1>;
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reg = <0xf0801000 0x1000>;
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0xf0000000 0x00300000>;
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timer0: timer@8000 {
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compatible = "nuvoton,npcm750-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x8000 0x1000>;
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clocks = <&clk 15>;
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};
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serial0: serial@1000 {
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compatible = "ns16550a";
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reg = <0x1000 0x1000>;
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clocks = <&clk 14>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial1: serial@2000 {
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compatible = "ns16550a";
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reg = <0x2000 0x1000>;
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clocks = <&clk 14>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial2: serial@3000 {
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compatible = "ns16550a";
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reg = <0x3000 0x1000>;
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clocks = <&clk 14>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial3: serial@4000 {
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compatible = "ns16550a";
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reg = <0x4000 0x1000>;
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clocks = <&clk 14>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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};
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};
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