ARM64: DT: Hisilicon hip05 and hip06 updates for 4.7
- Fix its node without msi-cells for hip05 - Add nor flash node for hip05 D02 board - Add initial dts for hip06 D03 board - Reorder and add the hip06 D03 binding in the binding document -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXINEDAAoJEAvIV27ZiWZcwQkQAIOSd4juC+23IfAOQHxdUANx 6nLxoAEFDqTA/mOLap1a7ttKTqlhRRPXepw8+mT+JqaNgd7oegXVWsoy7G+t6EGS 62piFNCY0V7PnpGyjSriN73Fup99RLKSbvhOvdn0zM1h2hlO5skSBj+ApVjTcclc ca+2ovMwdlUA3FIaIFjsFb+UDKju/VnShNBus2Uhb6dvdwHZ1jbTSKvfDd2PEcSy O0/E/DuZ7RyzpAaS93jy2Malhkl5ojw1O6svbXHD7/fgmQKHxIQSzXza0yKhO+fR Kx5zuoQxb2/Uwi/hI3lxmCWGJoht3jzlmqCYivP/FT3y+204MrcCyoZpCPN5jBhB todtfNRTWze5+8gEmPBPbCth3/4rAeWWbG1IObylNL8J4fxgQp5mUFHtAe8F3Q4v 6pcoXFynN2eKFCEXjw0G/E+3DjeAjaGiOtY+XnPnYvh4vQUqzFhxObEDi3gg4Rs5 SqHHpcV3n3lWv16kgSNbHP1I8RMFt44JwBchakzYrV+fz35JlFxiojCDumz5eotK s7dqGzAGNFzk0KxNi/Wwrn0dVPQk8FZfO9XuCb4Rl+ThO3VRKC6lhgP/S93sBYUk EgABmLJr/zv3TdymaMFAOcekWqBcwzTgQ7eGFGF20E5pvsUjCmtU3nFE6mG+IPoM kmrGprVN/53FrYX3DDaF =OZ3Q -----END PGP SIGNATURE----- Merge tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi into next/dt64 Merge "ARM64: DT: Hisilicon hip05 and hip06 updates for 4.7" Wei Xu: - Fix its node without msi-cells for hip05 - Add nor flash node for hip05 D02 board - Add initial dts for hip06 D03 board - Reorder and add the hip06 D03 binding in the binding document * tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi: Documentation: arm64: Add Hisilicon Hip06 D03 dts binding arm64: dts: Add initial dts for Hisilicon Hip06 D03 board arm64: dts: hip05: Add nor flash support arm64: dts: hip05: fix its node without msi-cells
This commit is contained in:
Arnd Bergmann
commit
d6a58a5cc1
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@ -1,29 +1,33 @@
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Hisilicon Platforms Device Tree Bindings
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----------------------------------------------------
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Hi6220 SoC
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Required root node properties:
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- compatible = "hisilicon,hi6220";
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Hi4511 Board
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Required root node properties:
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- compatible = "hisilicon,hi3620-hi4511";
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HiP04 D01 Board
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Hi6220 SoC
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Required root node properties:
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- compatible = "hisilicon,hip04-d01";
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HiP01 ca9x2 Board
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Required root node properties:
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- compatible = "hisilicon,hip01-ca9x2";
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- compatible = "hisilicon,hi6220";
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HiKey Board
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Required root node properties:
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- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
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HiP01 ca9x2 Board
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Required root node properties:
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- compatible = "hisilicon,hip01-ca9x2";
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HiP04 D01 Board
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Required root node properties:
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- compatible = "hisilicon,hip04-d01";
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HiP05 D02 Board
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Required root node properties:
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- compatible = "hisilicon,hip05-d02";
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HiP06 D03 Board
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Required root node properties:
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- compatible = "hisilicon,hip06-d03";
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Hisilicon system controller
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Required properties:
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@ -1,4 +1,6 @@
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dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb hip05-d02.dtb
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dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
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dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
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dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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@ -52,3 +52,37 @@
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&peri_gpio0 {
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status = "ok";
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};
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&lbc {
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status = "ok";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x0 0x90000000 0x08000000>,
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<1 0 0x0 0x98000000 0x08000000>;
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nor-flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "numonyx,js28f00a", "cfi-flash";
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reg = <0 0x0 0x08000000>;
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bank-width = <2>;
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/* The three parts may not used */
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partition@0 {
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label = "BIOS";
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reg = <0x0 0x300000>;
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};
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partition@300000 {
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label = "Linux";
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reg = <0x300000 0xa00000>;
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};
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partition@1000000 {
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label = "Rootfs";
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reg = <0x01000000 0x02000000>;
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};
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};
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cpld@1,0 {
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compatible = "hisilicon,hip05-cpld";
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reg = <1 0x0 0x100>;
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};
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};
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@ -249,24 +249,28 @@
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its_peri: interrupt-controller@8c000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x8c000000 0x0 0x40000>;
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};
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its_m3: interrupt-controller@a3000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0xa3000000 0x0 0x40000>;
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};
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its_pcie: interrupt-controller@b7000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0xb7000000 0x0 0x40000>;
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};
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its_dsa: interrupt-controller@c6000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0xc6000000 0x0 0x40000>;
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};
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};
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@ -323,6 +327,12 @@
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status = "disabled";
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};
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lbc: localbus@80380000 {
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compatible = "hisilicon,hisi-localbus", "simple-bus";
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reg = <0x0 0x80380000 0x0 0x10000>;
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status = "disabled";
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};
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peri_gpio0: gpio@802e0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -0,0 +1,34 @@
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/**
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* dts file for Hisilicon D03 Development Board
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*
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* Copyright (C) 2016 Hisilicon Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*
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*/
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/dts-v1/;
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#include "hip06.dtsi"
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/ {
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model = "Hisilicon Hip06 D03 Development Board";
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compatible = "hisilicon,hip06-d03";
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x00000000 0x0 0x40000000>;
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};
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chosen { };
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};
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&usb_ohci {
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status = "ok";
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};
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&usb_ehci {
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status = "ok";
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};
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@ -0,0 +1,307 @@
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/**
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* dts file for Hisilicon D03 Development Board
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*
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* Copyright (C) 2016 Hisilicon Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "hisilicon,hip06-d03";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu8>;
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};
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core1 {
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cpu = <&cpu9>;
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};
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core2 {
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cpu = <&cpu10>;
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};
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core3 {
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cpu = <&cpu11>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&cpu12>;
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};
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core1 {
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cpu = <&cpu13>;
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};
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core2 {
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cpu = <&cpu14>;
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};
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core3 {
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cpu = <&cpu15>;
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};
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};
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};
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cpu0: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10000>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu1: cpu@10001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10001>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu2: cpu@10002 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10002>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu3: cpu@10003 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10003>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu4: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10100>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu5: cpu@10101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10101>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu6: cpu@10102 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10102>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu7: cpu@10103 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10103>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu8: cpu@10200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10200>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu9: cpu@10201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10201>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu10: cpu@10202 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10202>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu11: cpu@10203 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10203>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu12: cpu@10300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10300>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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||||
};
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cpu13: cpu@10301 {
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||||
device_type = "cpu";
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||||
compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x10301>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cpu14: cpu@10302 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x10302>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cpu15: cpu@10303 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x10303>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
};
|
||||
|
||||
cluster0_l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
cluster1_l2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
cluster2_l2: l2-cache2 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
cluster3_l2: l2-cache3 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@4d000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x30000>;
|
||||
reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
|
||||
<0x0 0x4d100000 0 0x300000>, /* GICR */
|
||||
<0x0 0xfe000000 0 0x10000>, /* GICC */
|
||||
<0x0 0xfe010000 0 0x10000>, /* GICH */
|
||||
<0x0 0xfe020000 0 0x10000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
its_dsa: interrupt-controller@c6000000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x0 0xc6000000 0x0 0x40000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mbigen_pcie@a0080000 {
|
||||
compatible = "hisilicon,mbigen-v2";
|
||||
reg = <0x0 0xa0080000 0x0 0x10000>;
|
||||
|
||||
mbigen_usb: intc_usb {
|
||||
msi-parent = <&its_dsa 0x40080>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
num-pins = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
usb_ohci: ohci@a7030000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0xa7030000 0x0 0x10000>;
|
||||
interrupt-parent = <&mbigen_usb>;
|
||||
interrupts = <64 4>;
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_ehci: ehci@a7020000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xa7020000 0x0 0x10000>;
|
||||
interrupt-parent = <&mbigen_usb>;
|
||||
interrupts = <65 4>;
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
Loading…
Reference in New Issue