drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h
Move the TypeC DKL PHY register definitions to intel_dkl_phy_regs.h. No functional changes. v2: - Move the definitions to a new intel_dkl_phy_regs.h file. (Jani). v3: - Rebase on latest patchset version. Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221025114457.2191004-2-imre.deak@intel.com
This commit is contained in:
Imre Deak
parent
589ebefd7a
commit
d69813c764
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@ -44,6 +44,7 @@
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#include "intel_display_power.h"
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#include "intel_display_types.h"
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#include "intel_dkl_phy.h"
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#include "intel_dkl_phy_regs.h"
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#include "intel_dp.h"
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#include "intel_dp_link_training.h"
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#include "intel_dp_mst.h"
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@ -13,6 +13,7 @@
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#include "intel_display_power_well.h"
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#include "intel_display_types.h"
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#include "intel_dkl_phy.h"
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#include "intel_dkl_phy_regs.h"
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#include "intel_dmc.h"
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#include "intel_dpio_phy.h"
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#include "intel_dpll.h"
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@ -9,6 +9,7 @@
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#include "intel_de.h"
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#include "intel_display.h"
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#include "intel_dkl_phy.h"
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#include "intel_dkl_phy_regs.h"
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static void
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dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx)
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@ -0,0 +1,193 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_DKL_PHY_REGS__
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#define __INTEL_DKL_PHY_REGS__
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#define _DKL_PHY1_BASE 0x168000
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#define _DKL_PHY2_BASE 0x169000
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#define _DKL_PHY3_BASE 0x16A000
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#define _DKL_PHY4_BASE 0x16B000
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#define _DKL_PHY5_BASE 0x16C000
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#define _DKL_PHY6_BASE 0x16D000
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#define DKL_REG_TC_PORT(__reg) \
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(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
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/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
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#define _DKL_PCS_DW5 0x14
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#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PCS_DW5)
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#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11)
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#define _DKL_PLL_DIV0 0x200
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#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_DIV0)
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#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
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#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
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#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
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#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
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#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
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#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
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#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
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#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
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#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
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#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
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#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
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#define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \
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DKL_PLL_DIV0_PROP_COEFF_MASK | \
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DKL_PLL_DIV0_FBPREDIV_MASK | \
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DKL_PLL_DIV0_FBDIV_INT_MASK)
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#define _DKL_PLL_DIV1 0x204
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#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_DIV1)
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#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
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#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
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#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
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#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
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#define _DKL_PLL_SSC 0x210
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#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_SSC)
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#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
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#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
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#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
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#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
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#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
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#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
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#define DKL_PLL_SSC_EN (1 << 9)
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#define _DKL_PLL_BIAS 0x214
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#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_BIAS)
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#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
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#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
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#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
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#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
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#define _DKL_PLL_TDC_COLDST_BIAS 0x218
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#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_TDC_COLDST_BIAS)
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#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
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#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
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#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
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#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
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#define _DKL_REFCLKIN_CTL 0x12C
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#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_REFCLKIN_CTL)
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/* Bits are the same as MG_REFCLKIN_CTL */
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#define _DKL_CLKTOP2_HSCLKCTL 0xD4
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#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_CLKTOP2_HSCLKCTL)
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/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
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#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
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#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_CLKTOP2_CORECLKCTL1)
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/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
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#define _DKL_TX_DPCNTL0 0x2C0
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#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_TX_DPCNTL0)
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#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
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#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
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#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
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#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
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#define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
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#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
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#define _DKL_TX_DPCNTL1 0x2C4
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#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_TX_DPCNTL1)
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/* Bits are the same as DKL_TX_DPCNTRL0 */
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#define _DKL_TX_DPCNTL2 0x2C8
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#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_TX_DPCNTL2)
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#define DKL_TX_DP20BITMODE REG_BIT(2)
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
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#define _DKL_TX_FW_CALIB 0x2F8
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#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_TX_FW_CALIB)
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#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
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#define _DKL_TX_PMD_LANE_SUS 0xD00
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#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_TX_PMD_LANE_SUS)
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#define _DKL_TX_DW17 0xDC4
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#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_TX_DW17)
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#define _DKL_TX_DW18 0xDC8
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#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_TX_DW18)
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#define _DKL_DP_MODE 0xA0
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#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_DP_MODE)
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#define _DKL_CMN_UC_DW27 0x36C
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#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_CMN_UC_DW27)
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#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
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/*
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* Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
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* 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
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* or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
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* bits that point the 4KB window into the full PHY register space.
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*/
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#define _HIP_INDEX_REG0 0x1010A0
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#define _HIP_INDEX_REG1 0x1010A4
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#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
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: _HIP_INDEX_REG1)
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#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))
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#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
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#endif /* __INTEL_DKL_PHY_REGS__ */
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@ -26,6 +26,7 @@
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_dkl_phy.h"
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#include "intel_dkl_phy_regs.h"
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#include "intel_dpio_phy.h"
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#include "intel_dpll.h"
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#include "intel_dpll_mgr.h"
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@ -8,6 +8,7 @@
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#include "intel_display.h"
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#include "intel_display_power_map.h"
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#include "intel_display_types.h"
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#include "intel_dkl_phy_regs.h"
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#include "intel_dp_mst.h"
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#include "intel_mg_phy_regs.h"
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#include "intel_tc.h"
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@ -7418,185 +7418,6 @@ enum skl_power_gate {
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_ADLS_DPLL4_CFGCR1, \
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_ADLS_DPLL3_CFGCR1)
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#define _DKL_PHY1_BASE 0x168000
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#define _DKL_PHY2_BASE 0x169000
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#define _DKL_PHY3_BASE 0x16A000
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#define _DKL_PHY4_BASE 0x16B000
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#define _DKL_PHY5_BASE 0x16C000
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#define _DKL_PHY6_BASE 0x16D000
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#define DKL_REG_TC_PORT(__reg) \
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(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
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/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
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#define _DKL_PCS_DW5 0x14
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#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PCS_DW5)
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#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11)
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#define _DKL_PLL_DIV0 0x200
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#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
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#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
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#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
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#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
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#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
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#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
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#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
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#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
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#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
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#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
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#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
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#define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \
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DKL_PLL_DIV0_PROP_COEFF_MASK | \
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DKL_PLL_DIV0_FBPREDIV_MASK | \
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DKL_PLL_DIV0_FBDIV_INT_MASK)
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#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_DIV0)
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#define _DKL_PLL_DIV1 0x204
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#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
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#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
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#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
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#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
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#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_DIV1)
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#define _DKL_PLL_SSC 0x210
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#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
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#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
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#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
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#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
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#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
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#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
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#define DKL_PLL_SSC_EN (1 << 9)
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#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_SSC)
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#define _DKL_PLL_BIAS 0x214
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#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
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#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
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#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
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#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
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#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PLL_BIAS)
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#define _DKL_PLL_TDC_COLDST_BIAS 0x218
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#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
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#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
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#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
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#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
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#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_PLL_TDC_COLDST_BIAS)
|
||||
|
||||
#define _DKL_REFCLKIN_CTL 0x12C
|
||||
/* Bits are the same as MG_REFCLKIN_CTL */
|
||||
#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_REFCLKIN_CTL)
|
||||
|
||||
#define _DKL_CLKTOP2_HSCLKCTL 0xD4
|
||||
/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
|
||||
#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_CLKTOP2_HSCLKCTL)
|
||||
|
||||
#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
|
||||
/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
|
||||
#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_CLKTOP2_CORECLKCTL1)
|
||||
|
||||
#define _DKL_TX_DPCNTL0 0x2C0
|
||||
#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
|
||||
#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
|
||||
#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
|
||||
#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
|
||||
#define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
|
||||
#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
|
||||
#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DPCNTL0)
|
||||
|
||||
#define _DKL_TX_DPCNTL1 0x2C4
|
||||
/* Bits are the same as DKL_TX_DPCNTRL0 */
|
||||
#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DPCNTL1)
|
||||
|
||||
#define _DKL_TX_DPCNTL2 0x2C8
|
||||
#define DKL_TX_DP20BITMODE REG_BIT(2)
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
|
||||
#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DPCNTL2)
|
||||
|
||||
#define _DKL_TX_FW_CALIB 0x2F8
|
||||
#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
|
||||
#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_FW_CALIB)
|
||||
|
||||
#define _DKL_TX_PMD_LANE_SUS 0xD00
|
||||
#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_PMD_LANE_SUS)
|
||||
|
||||
#define _DKL_TX_DW17 0xDC4
|
||||
#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DW17)
|
||||
|
||||
#define _DKL_TX_DW18 0xDC8
|
||||
#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DW18)
|
||||
|
||||
#define _DKL_DP_MODE 0xA0
|
||||
#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_DP_MODE)
|
||||
|
||||
#define _DKL_CMN_UC_DW27 0x36C
|
||||
#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
|
||||
#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_CMN_UC_DW27)
|
||||
|
||||
/*
|
||||
* Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
|
||||
* 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
|
||||
* or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
|
||||
* bits that point the 4KB window into the full PHY register space.
|
||||
*/
|
||||
#define _HIP_INDEX_REG0 0x1010A0
|
||||
#define _HIP_INDEX_REG1 0x1010A4
|
||||
#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
|
||||
: _HIP_INDEX_REG1)
|
||||
#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))
|
||||
#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
|
||||
|
||||
/* BXT display engine PLL */
|
||||
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
|
||||
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
|
||||
|
|
|
|||
Loading…
Reference in New Issue