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tty: serial: fsl_lpuart: fix clearing of receive flag 

Commit 8e4934c6d6 ("tty: serial: fsl_lpuart: clear receive flag on FIFO
flush") implemented clearing of the receive flag by reading the status register
only. It turned out that even though we flush the FIFO afterwards, a explicit
read of the data register is still required.

This leads to a FIFO underrun. To avoid this, follow the advice in the overrun
"Operation section": Unconditionally clear RXUF after using RXFLUSH.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Stefan Agner 2016-07-19 13:13:05 +05:30 committed by Greg Kroah-Hartman
parent d6b0d2f243
commit d68827c62a
1 changed files with 6 additions and 3 deletions
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9
drivers/tty/serial/fsl_lpuart.c
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@ -935,13 +935,16 @@ static void lpuart_setup_watermark(struct lpuart_port *sport)
writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
sport->port.membase + UARTPFIFO);
/* explicitly clear RDRF */
readb(sport->port.membase + UARTSR1);
/* flush Tx and Rx FIFO */
writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
sport->port.membase + UARTCFIFO);
/* explicitly clear RDRF */
if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
readb(sport->port.membase + UARTDR);
writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
}
writeb(0, sport->port.membase + UARTTWFIFO);
writeb(1, sport->port.membase + UARTRWFIFO);