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MIPS: uasm: add MT ASE yield instruction 

This patch allows use of the MT ASE yield instruction from uasm. It will
be used by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton 2014-03-04 15:12:36 +00:00
parent 53ed138986
commit d674dd14e8
3 changed files with 11 additions and 1 deletions
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1
arch/mips/include/asm/uasm.h
View File

@ -150,6 +150,7 @@ Ip_0(_tlbwr);
Ip_u1(_wait);
Ip_u3u1u2(_xor);
Ip_u2u1u3(_xori);
Ip_u2u1(_yield);
/* Handle labels. */

1
arch/mips/mm/uasm-mips.c
View File

@ -116,6 +116,7 @@ static struct insn insn_table[] = {
{ insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },
{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
{ insn_yield, M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD },
{ insn_invalid, 0, 0 }
};

10
arch/mips/mm/uasm.c
View File

@ -54,7 +54,7 @@ enum opcode {
insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr,
insn_wait, insn_xor, insn_xori,
insn_wait, insn_xor, insn_xori, insn_yield,
};
struct insn {
@ -200,6 +200,13 @@ Ip_u1u2(op) \
} \
UASM_EXPORT_SYMBOL(uasm_i##op);
#define I_u2u1(op) \
Ip_u1u2(op) \
{ \
build_insn(buf, insn##op, b, a); \
} \
UASM_EXPORT_SYMBOL(uasm_i##op);
#define I_u1s2(op) \
Ip_u1s2(op) \
{ \
@ -279,6 +286,7 @@ I_0(_tlbwr)
I_u1(_wait);
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1(_yield)
I_u2u1msbu3(_dins);
I_u2u1msb32u3(_dinsm);
I_u1(_syscall);