MIPS: bcm3384: Initial commit of bcm3384 platform support
This supports SMP Linux running on the BCM3384 Zephyr (BMIPS5000) application processor, with fully functional UART and USB 1.1/2.0. Device Tree is used to configure the following items: - All peripherals - Early console base address - SMP or UP mode - MIPS counter frequency - Memory size / regions - DMA offset - Kernel command line The DT-enabled bootloader and build instructions are posted at https://github.com/Broadcom/aeolus Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8170/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Kevin Cernekee
Ralf Baechle
parent
ab81ce6217
commit
d666cd0246
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@ -3,6 +3,7 @@
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platforms += alchemy
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platforms += ar7
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platforms += ath79
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platforms += bcm3384
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platforms += bcm47xx
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platforms += bcm63xx
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platforms += cavium-octeon
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@ -116,6 +116,32 @@ config ATH79
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help
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Support for the Atheros AR71XX/AR724X/AR913X SoCs.
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config BCM3384
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bool "Broadcom BCM3384 based boards"
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select BOOT_RAW
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select NO_EXCEPT_FILL
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select USE_OF
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select CEVT_R4K
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select CSRC_R4K
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select SYNC_R4K
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select COMMON_CLK
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select DMA_NONCOHERENT
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select IRQ_CPU
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_HAS_CPU_BMIPS5000
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select SWAP_IO_SPACE
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select USB_EHCI_BIG_ENDIAN_DESC
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select USB_EHCI_BIG_ENDIAN_MMIO
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select USB_OHCI_BIG_ENDIAN_DESC
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select USB_OHCI_BIG_ENDIAN_MMIO
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help
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Support for BCM3384 based boards. BCM3384/BCM33843 is a cable modem
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chipset with a Linux application processor that is often used to
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provide Samba services, a CUPS print server, and/or advanced routing
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features.
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config BCM47XX
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bool "Broadcom BCM47XX based boards"
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select ARCH_WANT_OPTIONAL_GPIOLIB
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@ -0,0 +1 @@
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obj-y += setup.o irq.o dma.o
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@ -0,0 +1,7 @@
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#
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# Broadcom BCM3384 boards
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#
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platform-$(CONFIG_BCM3384) += bcm3384/
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cflags-$(CONFIG_BCM3384) += \
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-I$(srctree)/arch/mips/include/asm/mach-bcm3384/
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load-$(CONFIG_BCM3384) := 0xffffffff80010000
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@ -0,0 +1,81 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
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*/
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#include <linux/device.h>
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#include <linux/dma-direction.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <dma-coherence.h>
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/*
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* BCM3384 has configurable address translation windows which allow the
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* peripherals' DMA addresses to be different from the Zephyr-visible
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* physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
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*
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* If our DT "memory" node has a "dma-xor-mask" property we will enable this
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* translation using the provided offset.
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*/
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static u32 bcm3384_dma_xor_mask;
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static u32 bcm3384_dma_xor_limit = 0xffffffff;
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/*
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* PCI collapses the memory hole at 0x10000000 - 0x1fffffff.
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* On systems with a dma-xor-mask, this range is guaranteed to live above
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* the dma-xor-limit.
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*/
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#define BCM3384_MEM_HOLE_PA 0x10000000
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#define BCM3384_MEM_HOLE_SIZE 0x10000000
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static dma_addr_t bcm3384_phys_to_dma(struct device *dev, phys_addr_t pa)
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{
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if (dev && dev_is_pci(dev) &&
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pa >= (BCM3384_MEM_HOLE_PA + BCM3384_MEM_HOLE_SIZE))
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return pa - BCM3384_MEM_HOLE_SIZE;
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if (pa <= bcm3384_dma_xor_limit)
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return pa ^ bcm3384_dma_xor_mask;
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return pa;
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}
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dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
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{
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return bcm3384_phys_to_dma(dev, virt_to_phys(addr));
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}
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dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
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{
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return bcm3384_phys_to_dma(dev, page_to_phys(page));
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}
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unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
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{
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if (dev && dev_is_pci(dev) &&
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dma_addr >= BCM3384_MEM_HOLE_PA)
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return dma_addr + BCM3384_MEM_HOLE_SIZE;
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if ((dma_addr ^ bcm3384_dma_xor_mask) <= bcm3384_dma_xor_limit)
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return dma_addr ^ bcm3384_dma_xor_mask;
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return dma_addr;
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}
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static int __init bcm3384_init_dma_xor(void)
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{
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struct device_node *np = of_find_node_by_type(NULL, "memory");
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if (!np)
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return 0;
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of_property_read_u32(np, "dma-xor-mask", &bcm3384_dma_xor_mask);
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of_property_read_u32(np, "dma-xor-limit", &bcm3384_dma_xor_limit);
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of_node_put(np);
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return 0;
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}
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arch_initcall(bcm3384_init_dma_xor);
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@ -0,0 +1,193 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Partially based on arch/mips/ralink/irq.c
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
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*/
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/bmips.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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/* INTC register offsets */
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#define INTC_REG_ENABLE 0x00
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#define INTC_REG_STATUS 0x04
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#define MAX_WORDS 2
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#define IRQS_PER_WORD 32
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struct bcm3384_intc {
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int n_words;
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void __iomem *reg[MAX_WORDS];
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u32 enable[MAX_WORDS];
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spinlock_t lock;
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};
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static void bcm3384_intc_irq_unmask(struct irq_data *d)
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{
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struct bcm3384_intc *priv = d->domain->host_data;
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unsigned long flags;
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int idx = d->hwirq / IRQS_PER_WORD;
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int bit = d->hwirq % IRQS_PER_WORD;
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spin_lock_irqsave(&priv->lock, flags);
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priv->enable[idx] |= BIT(bit);
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__raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void bcm3384_intc_irq_mask(struct irq_data *d)
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{
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struct bcm3384_intc *priv = d->domain->host_data;
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unsigned long flags;
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int idx = d->hwirq / IRQS_PER_WORD;
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int bit = d->hwirq % IRQS_PER_WORD;
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spin_lock_irqsave(&priv->lock, flags);
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priv->enable[idx] &= ~BIT(bit);
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__raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static struct irq_chip bcm3384_intc_irq_chip = {
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.name = "INTC",
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.irq_unmask = bcm3384_intc_irq_unmask,
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.irq_mask = bcm3384_intc_irq_mask,
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.irq_mask_ack = bcm3384_intc_irq_mask,
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};
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unsigned int get_c0_compare_int(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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static void bcm3384_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_get_handler_data(irq);
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struct bcm3384_intc *priv = domain->host_data;
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unsigned long flags;
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unsigned int idx;
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for (idx = 0; idx < priv->n_words; idx++) {
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unsigned long pending;
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int hwirq;
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spin_lock_irqsave(&priv->lock, flags);
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pending = __raw_readl(priv->reg[idx] + INTC_REG_STATUS) &
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priv->enable[idx];
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spin_unlock_irqrestore(&priv->lock, flags);
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for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
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generic_handle_irq(irq_find_mapping(domain,
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hwirq + idx * IRQS_PER_WORD));
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}
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending =
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(read_c0_status() & read_c0_cause() & ST0_IM) >> STATUSB_IP0;
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int bit;
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for_each_set_bit(bit, &pending, 8)
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do_IRQ(MIPS_CPU_IRQ_BASE + bit);
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}
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static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &bcm3384_intc_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = intc_map,
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};
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static int __init ioremap_one_pair(struct bcm3384_intc *priv,
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struct device_node *node,
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int idx)
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{
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struct resource res;
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if (of_address_to_resource(node, idx, &res))
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return 0;
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if (request_mem_region(res.start, resource_size(&res),
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res.name) < 0)
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pr_err("Failed to request INTC register region\n");
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priv->reg[idx] = ioremap_nocache(res.start, resource_size(&res));
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if (!priv->reg[idx])
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panic("Failed to ioremap INTC register range");
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/* start up with everything masked before we hook the parent IRQ */
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__raw_writel(0, priv->reg[idx] + INTC_REG_ENABLE);
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priv->enable[idx] = 0;
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return IRQS_PER_WORD;
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}
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static int __init intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *domain;
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unsigned int parent_irq, n_irqs = 0;
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struct bcm3384_intc *priv;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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panic("Failed to allocate bcm3384_intc struct");
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spin_lock_init(&priv->lock);
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq)
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panic("Failed to get INTC IRQ");
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n_irqs += ioremap_one_pair(priv, node, 0);
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n_irqs += ioremap_one_pair(priv, node, 1);
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if (!n_irqs)
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panic("Failed to map INTC registers");
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priv->n_words = n_irqs / IRQS_PER_WORD;
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domain = irq_domain_add_linear(node, n_irqs, &irq_domain_ops, priv);
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if (!domain)
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panic("Failed to add irqdomain");
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irq_set_chained_handler(parent_irq, bcm3384_intc_irq_handler);
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irq_set_handler_data(parent_irq, domain);
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return 0;
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}
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static struct of_device_id of_irq_ids[] __initdata = {
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{ .compatible = "mti,cpu-interrupt-controller",
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.data = mips_cpu_intc_init },
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{ .compatible = "brcm,bcm3384-intc",
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.data = intc_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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bmips_tp1_irqs = 0;
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of_irq_init(of_irq_ids);
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}
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@ -0,0 +1,97 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
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*/
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/clk-provider.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/smp.h>
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#include <asm/addrspace.h>
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#include <asm/bmips.h>
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#include <asm/bootinfo.h>
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#include <asm/prom.h>
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#include <asm/smp-ops.h>
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#include <asm/time.h>
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void __init prom_init(void)
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{
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register_bmips_smp_ops();
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}
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void __init prom_free_prom_memory(void)
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{
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}
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const char *get_system_type(void)
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{
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return "BCM3384";
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}
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void __init plat_time_init(void)
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{
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struct device_node *np;
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u32 freq;
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np = of_find_node_by_name(NULL, "cpus");
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if (!np)
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panic("missing 'cpus' DT node");
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if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
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panic("missing 'mips-hpt-frequency' property");
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of_node_put(np);
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mips_hpt_frequency = freq;
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}
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void __init plat_mem_setup(void)
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{
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void *dtb = __dtb_start;
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set_io_port_base(0);
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
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if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
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dtb = phys_to_virt(fw_arg2);
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__dt_setup_arch(dtb);
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strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
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}
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void __init device_tree_init(void)
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{
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struct device_node *np;
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unflatten_and_copy_device_tree();
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/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
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np = of_find_node_by_name(NULL, "cpus");
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if (np && of_get_available_child_count(np) <= 1)
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bmips_smp_enabled = 0;
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of_node_put(np);
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}
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int __init plat_of_setup(void)
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{
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return __dt_register_buses("brcm,bcm3384", "simple-bus");
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}
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arch_initcall(plat_of_setup);
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static int __init plat_dev_init(void)
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{
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of_clk_init(NULL);
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return 0;
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}
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device_initcall(plat_dev_init);
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@ -1,3 +1,4 @@
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dtb-$(CONFIG_BCM3384) += bcm93384wvg.dtb
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dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
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dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb
|
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dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb
|
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@ -0,0 +1,109 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm3384", "brcm,bcm33843";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* On BMIPS5000 this is 1/8th of the CPU core clock */
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mips-hpt-frequency = <100000000>;
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||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
periph_clk: periph_clk@0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc@0 {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
periph_intc: periph_intc@14e00038 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
reg = <0x14e00038 0x8 0x14e00340 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
zmips_intc: zmips_intc@104b0060 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
reg = <0x104b0060 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <29>;
|
||||
};
|
||||
|
||||
iop_intc: iop_intc@14e00058 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
reg = <0x14e00058 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <6>;
|
||||
};
|
||||
|
||||
uart0: serial@14e00520 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x14e00520 0x18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <2>;
|
||||
clocks = <&periph_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@15400300 {
|
||||
compatible = "brcm,bcm3384-ehci", "generic-ehci";
|
||||
reg = <0x15400300 0x100>;
|
||||
big-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <41>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@15400400 {
|
||||
compatible = "brcm,bcm3384-ohci", "generic-ohci";
|
||||
reg = <0x15400400 0x100>;
|
||||
big-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <40>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm3384.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm93384wvg", "brcm,bcm3384";
|
||||
model = "Broadcom BCM93384WVG";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x04000000>;
|
||||
dma-xor-mask = <0x08000000>;
|
||||
dma-xor-limit = <0x0fffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
CONFIG_BCM3384=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=4
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_MIPS_O32_FP64_SUPPORT=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_RD_GZIP is not set
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_NL80211_TESTMODE=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
# CONFIG_BLK_DEV is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_USB_USBNET=y
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_EARLYCON_FORCE=y
|
||||
CONFIG_SERIAL_BCM63XX=y
|
||||
CONFIG_SERIAL_BCM63XX_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
|
||||
* Copyright (C) 2009 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_BCM3384_DMA_COHERENCE_H
|
||||
#define __ASM_MACH_BCM3384_DMA_COHERENCE_H
|
||||
|
||||
struct device;
|
||||
|
||||
extern dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size);
|
||||
extern dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page);
|
||||
extern unsigned long plat_dma_addr_to_phys(struct device *dev,
|
||||
dma_addr_t dma_addr);
|
||||
|
||||
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
|
||||
size_t size, enum dma_data_direction direction)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int plat_dma_supported(struct device *dev, u64 mask)
|
||||
{
|
||||
/*
|
||||
* we fall back to GFP_DMA when the mask isn't all 1s,
|
||||
* so we can't guarantee allocations that must be
|
||||
* within a tighter range than GFP_DMA..
|
||||
*/
|
||||
if (mask < DMA_BIT_MASK(24))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline int plat_device_is_coherent(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* __ASM_MACH_BCM3384_DMA_COHERENCE_H */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_BCM3384_WAR_H
|
||||
#define __ASM_MIPS_MACH_BCM3384_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_BCM3384_WAR_H */
|
||||
Loading…
Reference in New Issue