drm/i915/cnl: Add WaRsDisableCoarsePowerGating
Old Wa added now forever on CNL all steppings. With CPU P states enabled along with RC6, dispatcher hangs can happen. Cc: Rafael Antognolli <rafael.antognolli@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180222200535.9290-1-rodrigo.vivi@intel.com
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@ -2788,9 +2788,10 @@ intel_info(const struct drm_i915_private *dev_priv)
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/* Early gen2 have a totally busted CS tlb and require pinned batches. */
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#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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/* WaRsDisableCoarsePowerGating:skl,cnl */
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
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(IS_CANNONLAKE(dev_priv) || \
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IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
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/*
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* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
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@ -370,7 +370,7 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
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u32 action[2];
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action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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/* WaRsDisableCoarsePowerGating:skl,cnl */
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if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
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action[1] = 0;
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else
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@ -6715,7 +6715,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
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/*
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* 3b: Enable Coarse Power Gating only when RC6 is enabled.
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* WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
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* WaRsDisableCoarsePowerGating:skl,cnl - Render/Media PG need to be disabled with RC6.
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*/
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if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
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I915_WRITE(GEN9_PG_ENABLE, 0);
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