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ath9k: Fix temperature compensation 

The registers for temperature compensation need to
be programmed only for active chains. Use the TX chainmask
to make sure that this is done properly for QCA953x.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith Manoharan 2014-03-17 15:02:48 +05:30 committed by John W. Linville
parent c90d4f7bc5
commit d65b1278e3
1 changed files with 35 additions and 24 deletions
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59
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
View File

@ -4792,43 +4792,54 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah,
tempslope: tempslope:
if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4;
/* /*
* AR955x has tempSlope register for each chain. * AR955x has tempSlope register for each chain.
* Check whether temp_compensation feature is enabled or not. * Check whether temp_compensation feature is enabled or not.
*/ */
if (eep->baseEepHeader.featureEnable & 0x1) { if (eep->baseEepHeader.featureEnable & 0x1) {
if (frequency < 4000) { if (frequency < 4000) {
REG_RMW_FIELD(ah, AR_PHY_TPC_19, if (txmask & BIT(0))
AR_PHY_TPC_19_ALPHA_THERM, REG_RMW_FIELD(ah, AR_PHY_TPC_19,
eep->base_ext2.tempSlopeLow); AR_PHY_TPC_19_ALPHA_THERM,
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, eep->base_ext2.tempSlopeLow);
AR_PHY_TPC_19_ALPHA_THERM, if (txmask & BIT(1))
temp_slope); REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM,
AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
eep->base_ext2.tempSlopeHigh); if (txmask & BIT(2))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
AR_PHY_TPC_19_ALPHA_THERM,
eep->base_ext2.tempSlopeHigh);
} else { } else {
REG_RMW_FIELD(ah, AR_PHY_TPC_19, if (txmask & BIT(0))
AR_PHY_TPC_19_ALPHA_THERM, REG_RMW_FIELD(ah, AR_PHY_TPC_19,
temp_slope); AR_PHY_TPC_19_ALPHA_THERM,
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, temp_slope);
AR_PHY_TPC_19_ALPHA_THERM, if (txmask & BIT(1))
temp_slope1); REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM,
AR_PHY_TPC_19_ALPHA_THERM, temp_slope1);
temp_slope2); if (txmask & BIT(2))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
AR_PHY_TPC_19_ALPHA_THERM,
temp_slope2);
} }
} else { } else {
/* /*
* If temp compensation is not enabled, * If temp compensation is not enabled,
* set all registers to 0. * set all registers to 0.
*/ */
REG_RMW_FIELD(ah, AR_PHY_TPC_19, if (txmask & BIT(0))
AR_PHY_TPC_19_ALPHA_THERM, 0); REG_RMW_FIELD(ah, AR_PHY_TPC_19,
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, 0);
AR_PHY_TPC_19_ALPHA_THERM, 0); if (txmask & BIT(1))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
AR_PHY_TPC_19_ALPHA_THERM, 0); AR_PHY_TPC_19_ALPHA_THERM, 0);
if (txmask & BIT(2))
REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
AR_PHY_TPC_19_ALPHA_THERM, 0);
} }
} else { } else {
REG_RMW_FIELD(ah, AR_PHY_TPC_19, REG_RMW_FIELD(ah, AR_PHY_TPC_19,