drm/i915: Cleanup instdone collection
Consolidate the instdone logic so we can get a bit fancier. This patch also removes the duplicated print of INSTDONE[0]. v2: (Imre) - Rebased on top of hangcheck INSTDONE changes. - Move all INSTDONE registers into a single struct, store it within the engine error struct during error capturing. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1474379673-28326-1-git-send-email-imre.deak@intel.com
This commit is contained in:
Ben Widawsky
Imre Deak
parent
51f592050a
commit
d636951ec0
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@ -1277,15 +1277,36 @@ out:
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return ret;
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}
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static void i915_instdone_info(struct drm_i915_private *dev_priv,
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struct seq_file *m,
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struct intel_instdone *instdone)
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{
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seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
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instdone->instdone);
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if (INTEL_GEN(dev_priv) <= 3)
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return;
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seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
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instdone->slice_common);
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if (INTEL_GEN(dev_priv) <= 6)
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return;
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seq_printf(m, "\t\tSAMPLER_INSTDONE: 0x%08x\n",
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instdone->sampler);
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seq_printf(m, "\t\tROW_INSTDONE: 0x%08x\n",
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instdone->row);
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}
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static int i915_hangcheck_info(struct seq_file *m, void *unused)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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struct intel_engine_cs *engine;
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u64 acthd[I915_NUM_ENGINES];
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u32 seqno[I915_NUM_ENGINES];
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u32 instdone[I915_NUM_INSTDONE_REG];
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struct intel_instdone instdone;
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enum intel_engine_id id;
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int j;
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if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
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seq_printf(m, "Wedged\n");
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@ -1308,7 +1329,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
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seqno[id] = intel_engine_get_seqno(engine);
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}
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i915_get_extra_instdone(dev_priv, instdone);
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i915_get_engine_instdone(dev_priv, RCS, &instdone);
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intel_runtime_pm_put(dev_priv);
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@ -1336,18 +1357,14 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
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seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
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if (engine->id == RCS) {
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seq_puts(m, "\tinstdone read =");
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seq_puts(m, "\tinstdone read =\n");
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for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
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seq_printf(m, " 0x%08x", instdone[j]);
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i915_instdone_info(dev_priv, m, &instdone);
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seq_puts(m, "\n\tinstdone accu =");
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seq_puts(m, "\tinstdone accu =\n");
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for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
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seq_printf(m, " 0x%08x",
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engine->hangcheck.instdone[j]);
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seq_puts(m, "\n");
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i915_instdone_info(dev_priv, m,
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&engine->hangcheck.instdone);
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}
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}
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@ -759,7 +759,7 @@ struct drm_i915_error_state {
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u32 gam_ecochk;
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u32 gab_ctl;
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u32 gfx_mode;
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u32 extra_instdone[I915_NUM_INSTDONE_REG];
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u64 fence[I915_MAX_NUM_FENCES];
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struct intel_overlay_error_state *overlay;
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struct intel_display_error_state *display;
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@ -791,7 +791,6 @@ struct drm_i915_error_state {
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u32 hws;
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u32 ipeir;
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u32 ipehr;
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u32 instdone;
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u32 bbstate;
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u32 instpm;
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u32 instps;
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@ -802,6 +801,7 @@ struct drm_i915_error_state {
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u64 faddr;
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u32 rc_psmi; /* sleep state */
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u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
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struct intel_instdone instdone;
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struct drm_i915_error_object {
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int page_count;
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@ -3542,7 +3542,9 @@ void i915_error_state_get(struct drm_device *dev,
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void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
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void i915_destroy_error_state(struct drm_device *dev);
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void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
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void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
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enum intel_engine_id engine_id,
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struct intel_instdone *instdone);
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const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
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/* i915_cmd_parser.c */
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@ -228,6 +228,27 @@ static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
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return "unknown";
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}
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static void error_print_instdone(struct drm_i915_error_state_buf *m,
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struct drm_i915_error_engine *ee)
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{
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err_printf(m, " INSTDONE: 0x%08x\n",
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ee->instdone.instdone);
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if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
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return;
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err_printf(m, " SC_INSTDONE: 0x%08x\n",
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ee->instdone.slice_common);
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if (INTEL_GEN(m->i915) <= 6)
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return;
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err_printf(m, " SAMPLER_INSTDONE: 0x%08x\n",
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ee->instdone.sampler);
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err_printf(m, " ROW_INSTDONE: 0x%08x\n",
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ee->instdone.row);
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}
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static void error_print_engine(struct drm_i915_error_state_buf *m,
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struct drm_i915_error_engine *ee)
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{
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@ -242,7 +263,9 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
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(u32)(ee->acthd>>32), (u32)ee->acthd);
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err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
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err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
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err_printf(m, " INSTDONE: 0x%08x\n", ee->instdone);
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error_print_instdone(m, ee);
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if (ee->batchbuffer) {
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u64 start = ee->batchbuffer->gtt_offset;
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u64 end = start + ee->batchbuffer->gtt_size;
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@ -402,10 +425,6 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
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for (i = 0; i < dev_priv->num_fence_regs; i++)
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err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
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for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
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err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
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error->extra_instdone[i]);
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if (INTEL_INFO(dev)->gen >= 6) {
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err_printf(m, "ERROR: 0x%08x\n", error->error);
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@ -855,7 +874,8 @@ static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
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if (engine_id)
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*engine_id = i;
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return error->engine[i].ipehr ^ error->engine[i].instdone;
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return error->engine[i].ipehr ^
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error->engine[i].instdone.instdone;
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}
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}
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@ -998,7 +1018,6 @@ static void error_record_engine_registers(struct drm_i915_error_state *error,
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ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
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ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
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ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
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ee->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
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ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
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ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
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if (INTEL_GEN(dev_priv) >= 8) {
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@ -1010,9 +1029,10 @@ static void error_record_engine_registers(struct drm_i915_error_state *error,
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ee->faddr = I915_READ(DMA_FADD_I8XX);
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ee->ipeir = I915_READ(IPEIR);
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ee->ipehr = I915_READ(IPEHR);
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ee->instdone = I915_READ(GEN2_INSTDONE);
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}
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i915_get_engine_instdone(dev_priv, engine->id, &ee->instdone);
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ee->waiting = intel_engine_has_waiter(engine);
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ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
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ee->acthd = intel_engine_get_active_head(engine);
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@ -1372,8 +1392,6 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
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}
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error->eir = I915_READ(EIR);
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error->pgtbl_er = I915_READ(PGTBL_ER);
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i915_get_extra_instdone(dev_priv, error->extra_instdone);
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}
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static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
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@ -1532,20 +1550,38 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
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}
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/* NB: please notice the memset */
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void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
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uint32_t *instdone)
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void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
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enum intel_engine_id engine_id,
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struct intel_instdone *instdone)
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{
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memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
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u32 mmio_base = dev_priv->engine[engine_id].mmio_base;
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if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
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instdone[0] = I915_READ(GEN2_INSTDONE);
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else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
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instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
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instdone[1] = I915_READ(GEN4_INSTDONE1);
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} else if (INTEL_GEN(dev_priv) >= 7) {
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instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
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instdone[1] = I915_READ(GEN7_SC_INSTDONE);
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instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
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instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
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memset(instdone, 0, sizeof(*instdone));
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switch (INTEL_GEN(dev_priv)) {
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default:
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instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
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if (engine_id != RCS)
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break;
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instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
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instdone->sampler = I915_READ(GEN7_SAMPLER_INSTDONE);
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instdone->row = I915_READ(GEN7_ROW_INSTDONE);
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break;
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case 6:
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case 5:
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case 4:
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instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
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if (engine_id == RCS)
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/* HACK: Using the wrong struct member */
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instdone->slice_common = I915_READ(GEN4_INSTDONE1);
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break;
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case 3:
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case 2:
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instdone->instdone = I915_READ(GEN2_INSTDONE);
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break;
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}
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}
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@ -2545,18 +2545,36 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
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wake_up_all(&dev_priv->gpu_error.reset_queue);
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}
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static inline void
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i915_err_print_instdone(struct drm_i915_private *dev_priv,
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struct intel_instdone *instdone)
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{
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pr_err(" INSTDONE: 0x%08x\n", instdone->instdone);
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if (INTEL_GEN(dev_priv) <= 3)
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return;
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pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common);
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if (INTEL_GEN(dev_priv) <= 6)
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return;
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pr_err(" SAMPLER_INSTDONE: 0x%08x\n", instdone->sampler);
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pr_err(" ROW_INSTDONE: 0x%08x\n", instdone->row);
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}
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static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
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{
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uint32_t instdone[I915_NUM_INSTDONE_REG];
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struct intel_instdone instdone;
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u32 eir = I915_READ(EIR);
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int pipe, i;
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int pipe;
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if (!eir)
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return;
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pr_err("render error detected, EIR: 0x%08x\n", eir);
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i915_get_extra_instdone(dev_priv, instdone);
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i915_get_engine_instdone(dev_priv, RCS, &instdone);
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if (IS_G4X(dev_priv)) {
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if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
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@ -2564,8 +2582,7 @@ static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
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pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
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pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
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for (i = 0; i < ARRAY_SIZE(instdone); i++)
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pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
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i915_err_print_instdone(dev_priv, &instdone);
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pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
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pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
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I915_WRITE(IPEIR_I965, ipeir);
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@ -2600,8 +2617,7 @@ static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
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if (eir & I915_ERROR_INSTRUCTION) {
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pr_err("instruction error\n");
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pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
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for (i = 0; i < ARRAY_SIZE(instdone); i++)
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pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
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i915_err_print_instdone(dev_priv, &instdone);
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if (INTEL_GEN(dev_priv) < 4) {
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u32 ipeir = I915_READ(IPEIR);
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@ -2948,31 +2964,42 @@ static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
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engine->hangcheck.deadlock = 0;
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}
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static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
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{
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u32 tmp = current_instdone | *old_instdone;
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bool unchanged;
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unchanged = tmp == *old_instdone;
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*old_instdone |= tmp;
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return unchanged;
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}
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static bool subunits_stuck(struct intel_engine_cs *engine)
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{
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u32 instdone[I915_NUM_INSTDONE_REG];
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_instdone instdone;
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struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
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bool stuck;
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int i;
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if (engine->id != RCS)
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return true;
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i915_get_extra_instdone(engine->i915, instdone);
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i915_get_engine_instdone(dev_priv, RCS, &instdone);
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/* There might be unstable subunit states even when
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* actual head is not moving. Filter out the unstable ones by
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* accumulating the undone -> done transitions and only
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* consider those as progress.
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*/
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stuck = true;
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for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
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const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
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if (tmp != engine->hangcheck.instdone[i])
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stuck = false;
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engine->hangcheck.instdone[i] |= tmp;
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}
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stuck = instdone_unchanged(instdone.instdone,
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&accu_instdone->instdone);
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stuck &= instdone_unchanged(instdone.slice_common,
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&accu_instdone->slice_common);
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stuck &= instdone_unchanged(instdone.sampler,
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&accu_instdone->sampler);
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stuck &= instdone_unchanged(instdone.row,
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&accu_instdone->row);
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return stuck;
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}
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@ -2983,7 +3010,7 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
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if (acthd != engine->hangcheck.acthd) {
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/* Clear subunit states on head movement */
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memset(engine->hangcheck.instdone, 0,
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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return HANGCHECK_ACTIVE;
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@ -3153,7 +3180,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
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/* Clear head and subunit states on seqno movement */
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acthd = 0;
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memset(engine->hangcheck.instdone, 0,
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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}
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@ -1708,7 +1708,6 @@ enum skl_disp_power_wells {
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|||
#define GEN7_SC_INSTDONE _MMIO(0x7100)
|
||||
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
|
||||
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
|
||||
#define I915_NUM_INSTDONE_REG 4
|
||||
#define RING_IPEIR(base) _MMIO((base)+0x64)
|
||||
#define RING_IPEHR(base) _MMIO((base)+0x68)
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -73,13 +73,21 @@ enum intel_engine_hangcheck_action {
|
|||
|
||||
#define HANGCHECK_SCORE_RING_HUNG 31
|
||||
|
||||
struct intel_instdone {
|
||||
u32 instdone;
|
||||
/* The following exist only in the RCS engine */
|
||||
u32 slice_common;
|
||||
u32 sampler;
|
||||
u32 row;
|
||||
};
|
||||
|
||||
struct intel_engine_hangcheck {
|
||||
u64 acthd;
|
||||
u32 seqno;
|
||||
int score;
|
||||
enum intel_engine_hangcheck_action action;
|
||||
int deadlock;
|
||||
u32 instdone[I915_NUM_INSTDONE_REG];
|
||||
struct intel_instdone instdone;
|
||||
};
|
||||
|
||||
struct intel_ring {
|
||||
|
|
|
|||
Loading…
Reference in New Issue