kvm/x86: per-vcpu apicv deactivation support
The decision on whether to use hardware APIC virtualization used to be taken globally, based on the availability of the feature in the CPU and the value of a module parameter. However, under certain circumstances we want to control it on per-vcpu basis. In particular, when the userspace activates HyperV synthetic interrupt controller (SynIC), APICv has to be disabled as it's incompatible with SynIC auto-EOI behavior. To achieve that, introduce 'apicv_active' flag on struct kvm_vcpu_arch, and kvm_vcpu_deactivate_apicv() function to turn APICv off. The flag is initialized based on the module parameter and CPU capability, and consulted whenever an APICv-specific action is performed. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Gleb Natapov <gleb@kernel.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: qemu-devel@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Andrey Smetanin
Paolo Bonzini
parent
6308630bd3
commit
d62caabb41
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@ -400,6 +400,7 @@ struct kvm_vcpu_arch {
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u64 efer;
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u64 apic_base;
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struct kvm_lapic *apic; /* kernel irqchip context */
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bool apicv_active;
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DECLARE_BITMAP(ioapic_handled_vectors, 256);
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unsigned long apic_attention;
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int32_t apic_arb_prio;
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@ -831,7 +832,8 @@ struct kvm_x86_ops {
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void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
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void (*enable_irq_window)(struct kvm_vcpu *vcpu);
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void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
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int (*cpu_uses_apicv)(struct kvm_vcpu *vcpu);
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bool (*get_enable_apicv)(void);
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void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
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void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
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void (*hwapic_isr_update)(struct kvm *kvm, int isr);
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void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
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@ -1086,6 +1088,8 @@ gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
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gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
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struct x86_exception *exception);
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void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu);
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int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
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int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code,
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@ -76,7 +76,7 @@ int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v)
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if (kvm_cpu_has_extint(v))
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return 1;
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if (kvm_vcpu_apic_vid_enabled(v))
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if (kvm_vcpu_apicv_active(v))
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return 0;
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return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
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@ -379,7 +379,8 @@ static inline int apic_find_highest_irr(struct kvm_lapic *apic)
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if (!apic->irr_pending)
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return -1;
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kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
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if (apic->vcpu->arch.apicv_active)
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kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
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result = apic_search_irr(apic);
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ASSERT(result == -1 || result >= 16);
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@ -392,7 +393,7 @@ static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
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vcpu = apic->vcpu;
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if (unlikely(kvm_vcpu_apic_vid_enabled(vcpu))) {
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if (unlikely(vcpu->arch.apicv_active)) {
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/* try to update RVI */
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apic_clear_vector(vec, apic->regs + APIC_IRR);
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kvm_make_request(KVM_REQ_EVENT, vcpu);
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@ -418,7 +419,7 @@ static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
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* because the processor can modify ISR under the hood. Instead
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* just set SVI.
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*/
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if (unlikely(kvm_x86_ops->hwapic_isr_update))
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if (unlikely(vcpu->arch.apicv_active))
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kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
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else {
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++apic->isr_count;
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@ -466,7 +467,7 @@ static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
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* on the other hand isr_count and highest_isr_cache are unused
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* and must be left alone.
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*/
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if (unlikely(kvm_x86_ops->hwapic_isr_update))
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if (unlikely(vcpu->arch.apicv_active))
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kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
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apic_find_highest_isr(apic));
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else {
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@ -852,7 +853,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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apic_clear_vector(vector, apic->regs + APIC_TMR);
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}
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if (kvm_x86_ops->deliver_posted_interrupt)
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if (vcpu->arch.apicv_active)
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kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
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else {
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apic_set_irr(vector, apic);
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@ -1225,7 +1226,7 @@ static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
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int vec = reg & APIC_VECTOR_MASK;
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void *bitmap = apic->regs + APIC_ISR;
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if (kvm_x86_ops->deliver_posted_interrupt)
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if (vcpu->arch.apicv_active)
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bitmap = apic->regs + APIC_IRR;
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if (apic_test_vector(vec, bitmap))
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@ -1693,8 +1694,8 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
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apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
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apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
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}
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apic->irr_pending = kvm_vcpu_apic_vid_enabled(vcpu);
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apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
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apic->irr_pending = vcpu->arch.apicv_active;
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apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
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apic->highest_isr_cache = -1;
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update_divide_count(apic);
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atomic_set(&apic->lapic_timer.pending, 0);
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@ -1906,15 +1907,15 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
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update_divide_count(apic);
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start_apic_timer(apic);
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apic->irr_pending = true;
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apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
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apic->isr_count = vcpu->arch.apicv_active ?
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1 : count_vectors(apic->regs + APIC_ISR);
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apic->highest_isr_cache = -1;
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if (kvm_x86_ops->hwapic_irr_update)
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if (vcpu->arch.apicv_active) {
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kvm_x86_ops->hwapic_irr_update(vcpu,
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apic_find_highest_irr(apic));
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if (unlikely(kvm_x86_ops->hwapic_isr_update))
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kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
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apic_find_highest_isr(apic));
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}
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kvm_make_request(KVM_REQ_EVENT, vcpu);
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if (ioapic_in_kernel(vcpu->kvm))
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kvm_rtc_eoi_tracking_restore_one(vcpu);
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@ -143,9 +143,9 @@ static inline int apic_x2apic_mode(struct kvm_lapic *apic)
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return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
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}
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static inline bool kvm_vcpu_apic_vid_enabled(struct kvm_vcpu *vcpu)
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static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
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{
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return kvm_x86_ops->cpu_uses_apicv(vcpu);
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return vcpu->arch.apic && vcpu->arch.apicv_active;
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}
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static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
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@ -3559,9 +3559,13 @@ static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
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return;
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}
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static int svm_cpu_uses_apicv(struct kvm_vcpu *vcpu)
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static bool svm_get_enable_apicv(void)
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{
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return false;
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}
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static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
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@ -4328,7 +4332,8 @@ static struct kvm_x86_ops svm_x86_ops = {
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.enable_irq_window = enable_irq_window,
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.update_cr8_intercept = update_cr8_intercept,
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.set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
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.cpu_uses_apicv = svm_cpu_uses_apicv,
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.get_enable_apicv = svm_get_enable_apicv,
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.refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
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.load_eoi_exitmap = svm_load_eoi_exitmap,
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.sync_pir_to_irr = svm_sync_pir_to_irr,
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@ -19,6 +19,7 @@
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#include "irq.h"
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#include "mmu.h"
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#include "cpuid.h"
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#include "lapic.h"
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#include <linux/kvm_host.h>
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#include <linux/module.h>
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@ -862,7 +863,6 @@ static void kvm_cpu_vmxon(u64 addr);
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static void kvm_cpu_vmxoff(void);
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static bool vmx_mpx_supported(void);
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static bool vmx_xsaves_supported(void);
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static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
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static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
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static void vmx_set_segment(struct kvm_vcpu *vcpu,
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struct kvm_segment *var, int seg);
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@ -870,7 +870,6 @@ static void vmx_get_segment(struct kvm_vcpu *vcpu,
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struct kvm_segment *var, int seg);
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static bool guest_state_valid(struct kvm_vcpu *vcpu);
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static u32 vmx_segment_access_rights(struct kvm_segment *var);
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static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
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static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
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static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
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static int alloc_identity_pagetable(struct kvm *kvm);
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@ -2498,7 +2497,7 @@ static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
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vmx->nested.nested_vmx_pinbased_ctls_high |=
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PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
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PIN_BASED_VMX_PREEMPTION_TIMER;
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if (vmx_cpu_uses_apicv(&vmx->vcpu))
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if (kvm_vcpu_apicv_active(&vmx->vcpu))
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vmx->nested.nested_vmx_pinbased_ctls_high |=
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PIN_BASED_POSTED_INTR;
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@ -4462,9 +4461,9 @@ static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
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msr, MSR_TYPE_W);
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}
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static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
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static bool vmx_get_enable_apicv(void)
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{
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return enable_apicv && lapic_in_kernel(vcpu);
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return enable_apicv;
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}
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static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
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@ -4586,11 +4585,6 @@ static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
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kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
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}
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static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
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{
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return;
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}
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/*
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* Set up the vmcs's constant host-state fields, i.e., host-state fields that
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* will not change in the lifetime of the guest.
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@ -4660,11 +4654,18 @@ static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
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{
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u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
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if (!vmx_cpu_uses_apicv(&vmx->vcpu))
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if (!kvm_vcpu_apicv_active(&vmx->vcpu))
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pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
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return pin_based_exec_ctrl;
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}
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static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
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}
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static u32 vmx_exec_control(struct vcpu_vmx *vmx)
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{
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u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
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@ -4703,7 +4704,7 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
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exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
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if (!ple_gap)
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exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
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if (!vmx_cpu_uses_apicv(&vmx->vcpu))
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if (!kvm_vcpu_apicv_active(&vmx->vcpu))
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exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
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SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
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exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
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@ -4767,7 +4768,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
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vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
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vmx_secondary_exec_control(vmx));
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if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
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if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
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vmcs_write64(EOI_EXIT_BITMAP0, 0);
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vmcs_write64(EOI_EXIT_BITMAP1, 0);
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vmcs_write64(EOI_EXIT_BITMAP2, 0);
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@ -4919,7 +4920,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
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kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
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if (vmx_cpu_uses_apicv(vcpu))
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if (kvm_vcpu_apicv_active(vcpu))
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memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
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if (vmx->vpid != 0)
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@ -6203,15 +6204,6 @@ static __init int hardware_setup(void)
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kvm_tsc_scaling_ratio_frac_bits = 48;
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}
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if (enable_apicv)
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kvm_x86_ops->update_cr8_intercept = NULL;
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else {
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kvm_x86_ops->hwapic_irr_update = NULL;
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kvm_x86_ops->hwapic_isr_update = NULL;
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kvm_x86_ops->deliver_posted_interrupt = NULL;
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kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
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}
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vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
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vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
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vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
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@ -8152,7 +8144,7 @@ static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
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* apicv
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*/
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if (!cpu_has_vmx_virtualize_x2apic_mode() ||
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!vmx_cpu_uses_apicv(vcpu))
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!kvm_vcpu_apicv_active(vcpu))
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return;
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if (!cpu_need_tpr_shadow(vcpu))
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@ -8259,7 +8251,7 @@ static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
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static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
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{
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if (!vmx_cpu_uses_apicv(vcpu))
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if (!kvm_vcpu_apicv_active(vcpu))
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return;
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vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
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@ -10803,7 +10795,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
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.update_cr8_intercept = update_cr8_intercept,
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.set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
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.set_apic_access_page_addr = vmx_set_apic_access_page_addr,
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.cpu_uses_apicv = vmx_cpu_uses_apicv,
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.get_enable_apicv = vmx_get_enable_apicv,
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.refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
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.load_eoi_exitmap = vmx_load_eoi_exitmap,
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.hwapic_irr_update = vmx_hwapic_irr_update,
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.hwapic_isr_update = vmx_hwapic_isr_update,
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@ -2748,7 +2748,9 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
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static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
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struct kvm_lapic_state *s)
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{
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kvm_x86_ops->sync_pir_to_irr(vcpu);
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if (vcpu->arch.apicv_active)
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kvm_x86_ops->sync_pir_to_irr(vcpu);
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memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
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return 0;
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@ -5867,6 +5869,12 @@ static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
|
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kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
|
||||
}
|
||||
|
||||
void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
vcpu->arch.apicv_active = false;
|
||||
kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
|
||||
}
|
||||
|
||||
int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
unsigned long nr, a0, a1, a2, a3, ret;
|
||||
|
|
@ -5960,6 +5968,9 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu)
|
|||
if (!vcpu->arch.apic)
|
||||
return;
|
||||
|
||||
if (vcpu->arch.apicv_active)
|
||||
return;
|
||||
|
||||
if (!vcpu->arch.apic->vapic_addr)
|
||||
max_irr = kvm_lapic_find_highest_irr(vcpu);
|
||||
else
|
||||
|
|
@ -6306,7 +6317,8 @@ static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
|
|||
if (irqchip_split(vcpu->kvm))
|
||||
kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
|
||||
else {
|
||||
kvm_x86_ops->sync_pir_to_irr(vcpu);
|
||||
if (vcpu->arch.apicv_active)
|
||||
kvm_x86_ops->sync_pir_to_irr(vcpu);
|
||||
kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
|
||||
}
|
||||
kvm_x86_ops->load_eoi_exitmap(vcpu,
|
||||
|
|
@ -6453,7 +6465,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
|
|||
* Update architecture specific hints for APIC
|
||||
* virtual interrupt delivery.
|
||||
*/
|
||||
if (kvm_x86_ops->hwapic_irr_update)
|
||||
if (vcpu->arch.apicv_active)
|
||||
kvm_x86_ops->hwapic_irr_update(vcpu,
|
||||
kvm_lapic_find_highest_irr(vcpu));
|
||||
}
|
||||
|
|
@ -7524,6 +7536,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
|
|||
BUG_ON(vcpu->kvm == NULL);
|
||||
kvm = vcpu->kvm;
|
||||
|
||||
vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
|
||||
vcpu->arch.pv.pv_unhalted = false;
|
||||
vcpu->arch.emulate_ctxt.ops = &emulate_ops;
|
||||
if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
|
||||
|
|
|
|||
Loading…
Reference in New Issue