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ARM: dts: uniphier: Add ahci controller nodes for Pro4 

Add ahci controller, glue layer, and clock nodes for Pro4 SoC. The glue
layer includes reset and phy, and the clock node is used for handling ahci
clocks on SoC-glue.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-7-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Kunihiko Hayashi 2022-09-13 13:22:46 +09:00 committed by Arnd Bergmann
parent c9c50dfdf6
commit d5566de59b
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GPG Key ID: 9A6C79EFE60018D9
3 changed files with 113 additions and 0 deletions
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8
arch/arm/boot/dts/uniphier-pro4-ace.dts
View File

@ -99,3 +99,11 @@
&usb1 {
status = "okay";
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};

8
arch/arm/boot/dts/uniphier-pro4-ref.dts
View File

@ -108,3 +108,11 @@
reg = <0>;
};
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};

97
arch/arm/boot/dts/uniphier-pro4.dtsi
View File

@ -411,6 +411,11 @@
vbus-supply = <&usb1_vbus>;
};
};
sg_clk: clock {
compatible = "socionext,uniphier-pro4-sg-clock";
#clock-cells = <1>;
};
};
soc-glue@5f900000 {
@ -513,6 +518,98 @@
};
};
ahci0: sata@65600000 {
compatible = "socionext,uniphier-pro4-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65600000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 12>, <&sys_clk 28>;
resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
ports-implemented = <1>;
phys = <&ahci0_phy>;
assigned-clocks = <&sg_clk 0>;
assigned-clock-rates = <25000000>;
};
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs2-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
ahci0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro4-ahci-reset";
reg = <0x0 0x4>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 28>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 28>;
#reset-cells = <1>;
};
ahci0_phy: sata-phy@10 {
compatible = "socionext,uniphier-pro4-ahci-phy";
reg = <0x10 0x40>;
clock-names = "link", "gio";
clocks = <&sys_clk 28>, <&sys_clk 12>;
reset-names = "link", "gio", "phy",
"pm", "tx", "rx";
resets = <&sys_rst 28>, <&sys_rst 12>,
<&sys_rst 30>,
<&ahci0_rst 0>, <&ahci0_rst 1>,
<&ahci0_rst 2>;
#phy-cells = <0>;
};
};
ahci1: sata@65800000 {
compatible = "socionext,uniphier-pro4-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65800000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 12>, <&sys_clk 29>;
resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
ports-implemented = <1>;
phys = <&ahci1_phy>;
assigned-clocks = <&sg_clk 0>;
assigned-clock-rates = <25000000>;
};
sata-controller@65900000 {
compatible = "socionext,uniphier-pro4-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65900000 0x100>;
ahci1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro4-ahci-reset";
reg = <0x0 0x4>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 29>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 29>;
#reset-cells = <1>;
};
ahci1_phy: sata-phy@10 {
compatible = "socionext,uniphier-pro4-ahci-phy";
reg = <0x10 0x40>;
clock-names = "link", "gio";
clocks = <&sys_clk 29>, <&sys_clk 12>;
reset-names = "link", "gio", "phy",
"pm", "tx", "rx";
resets = <&sys_rst 29>, <&sys_rst 12>,
<&sys_rst 30>,
<&ahci1_rst 0>, <&ahci1_rst 1>,
<&ahci1_rst 2>;
#phy-cells = <0>;
};
};
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";