ARM: IOMMU: Tegra20: Add iommu_ops for GART driver
Tegra 20 IOMMU H/W, GART (Graphics Address Relocation Table). This patch implements struct iommu_ops for GART for the upper IOMMU API. This H/W module supports only single virtual address space(domain), and manages a single level 1-to-1 mapping H/W translation page table. [With small fixes by Joerg Roedel] Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Hiroshi DOYU
Joerg Roedel
parent
dcd6c92267
commit
d53e54b4d4
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@ -142,4 +142,14 @@ config OMAP_IOMMU_DEBUG
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Say N unless you know you need this.
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config TEGRA_IOMMU_GART
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bool "Tegra GART IOMMU Support"
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depends on ARCH_TEGRA_2x_SOC
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select IOMMU_API
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help
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Enables support for remapping discontiguous physical memory
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shared with the operating system into contiguous I/O virtual
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space through the GART (Graphics Address Relocation Table)
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hardware included on Tegra SoCs.
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endif # IOMMU_SUPPORT
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@ -8,3 +8,4 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o
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obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
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obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
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obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
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obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
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@ -0,0 +1,451 @@
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/*
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* IOMMU API for GART in Tegra20
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*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#define pr_fmt(fmt) "%s(): " fmt, __func__
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/mm.h>
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#include <linux/list.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <asm/cacheflush.h>
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/* bitmap of the page sizes currently supported */
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#define GART_IOMMU_PGSIZES (SZ_4K)
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#define GART_CONFIG 0x24
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#define GART_ENTRY_ADDR 0x28
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#define GART_ENTRY_DATA 0x2c
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#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)
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#define GART_PAGE_SHIFT 12
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#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT)
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#define GART_PAGE_MASK \
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(~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID)
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struct gart_client {
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struct device *dev;
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struct list_head list;
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};
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struct gart_device {
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void __iomem *regs;
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u32 *savedata;
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u32 page_count; /* total remappable size */
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dma_addr_t iovmm_base; /* offset to vmm_area */
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spinlock_t pte_lock; /* for pagetable */
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struct list_head client;
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spinlock_t client_lock; /* for client list */
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struct device *dev;
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};
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static struct gart_device *gart_handle; /* unique for a system */
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#define GART_PTE(_pfn) \
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(GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT))
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/*
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* Any interaction between any block on PPSB and a block on APB or AHB
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* must have these read-back to ensure the APB/AHB bus transaction is
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* complete before initiating activity on the PPSB block.
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*/
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#define FLUSH_GART_REGS(gart) ((void)readl((gart)->regs + GART_CONFIG))
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#define for_each_gart_pte(gart, iova) \
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for (iova = gart->iovmm_base; \
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iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
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iova += GART_PAGE_SIZE)
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static inline void gart_set_pte(struct gart_device *gart,
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unsigned long offs, u32 pte)
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{
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writel(offs, gart->regs + GART_ENTRY_ADDR);
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writel(pte, gart->regs + GART_ENTRY_DATA);
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dev_dbg(gart->dev, "%s %08lx:%08x\n",
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pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK);
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}
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static inline unsigned long gart_read_pte(struct gart_device *gart,
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unsigned long offs)
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{
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unsigned long pte;
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writel(offs, gart->regs + GART_ENTRY_ADDR);
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pte = readl(gart->regs + GART_ENTRY_DATA);
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return pte;
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}
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static void do_gart_setup(struct gart_device *gart, const u32 *data)
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{
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unsigned long iova;
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for_each_gart_pte(gart, iova)
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gart_set_pte(gart, iova, data ? *(data++) : 0);
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writel(1, gart->regs + GART_CONFIG);
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FLUSH_GART_REGS(gart);
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}
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#ifdef DEBUG
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static void gart_dump_table(struct gart_device *gart)
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{
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unsigned long iova;
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unsigned long flags;
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spin_lock_irqsave(&gart->pte_lock, flags);
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for_each_gart_pte(gart, iova) {
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unsigned long pte;
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pte = gart_read_pte(gart, iova);
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dev_dbg(gart->dev, "%s %08lx:%08lx\n",
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(GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ",
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iova, pte & GART_PAGE_MASK);
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}
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spin_unlock_irqrestore(&gart->pte_lock, flags);
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}
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#else
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static inline void gart_dump_table(struct gart_device *gart)
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{
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}
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#endif
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static inline bool gart_iova_range_valid(struct gart_device *gart,
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unsigned long iova, size_t bytes)
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{
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unsigned long iova_start, iova_end, gart_start, gart_end;
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iova_start = iova;
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iova_end = iova_start + bytes - 1;
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gart_start = gart->iovmm_base;
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gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1;
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if (iova_start < gart_start)
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return false;
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if (iova_end > gart_end)
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return false;
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return true;
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}
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static int gart_iommu_attach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct gart_device *gart;
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struct gart_client *client, *c;
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int err = 0;
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gart = dev_get_drvdata(dev->parent);
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if (!gart)
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return -EINVAL;
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domain->priv = gart;
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client = devm_kzalloc(gart->dev, sizeof(*c), GFP_KERNEL);
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if (!client)
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return -ENOMEM;
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client->dev = dev;
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spin_lock(&gart->client_lock);
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list_for_each_entry(c, &gart->client, list) {
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if (c->dev == dev) {
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dev_err(gart->dev,
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"%s is already attached\n", dev_name(dev));
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err = -EINVAL;
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goto fail;
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}
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}
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list_add(&client->list, &gart->client);
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spin_unlock(&gart->client_lock);
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dev_dbg(gart->dev, "Attached %s\n", dev_name(dev));
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return 0;
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fail:
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devm_kfree(gart->dev, client);
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spin_unlock(&gart->client_lock);
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return err;
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}
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static void gart_iommu_detach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct gart_device *gart = domain->priv;
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struct gart_client *c;
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spin_lock(&gart->client_lock);
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list_for_each_entry(c, &gart->client, list) {
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if (c->dev == dev) {
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list_del(&c->list);
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devm_kfree(gart->dev, c);
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dev_dbg(gart->dev, "Detached %s\n", dev_name(dev));
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goto out;
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}
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}
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dev_err(gart->dev, "Couldn't find\n");
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out:
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spin_unlock(&gart->client_lock);
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}
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static int gart_iommu_domain_init(struct iommu_domain *domain)
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{
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return 0;
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}
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static void gart_iommu_domain_destroy(struct iommu_domain *domain)
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{
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struct gart_device *gart = domain->priv;
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if (!gart)
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return;
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spin_lock(&gart->client_lock);
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if (!list_empty(&gart->client)) {
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struct gart_client *c;
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list_for_each_entry(c, &gart->client, list)
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gart_iommu_detach_dev(domain, c->dev);
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}
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spin_unlock(&gart->client_lock);
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domain->priv = NULL;
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}
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static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t pa, size_t bytes, int prot)
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{
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struct gart_device *gart = domain->priv;
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unsigned long flags;
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unsigned long pfn;
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if (!gart_iova_range_valid(gart, iova, bytes))
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return -EINVAL;
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spin_lock_irqsave(&gart->pte_lock, flags);
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pfn = __phys_to_pfn(pa);
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if (!pfn_valid(pfn)) {
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dev_err(gart->dev, "Invalid page: %08x\n", pa);
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spin_lock_irqsave(&gart->pte_lock, flags);
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return -EINVAL;
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}
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gart_set_pte(gart, iova, GART_PTE(pfn));
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FLUSH_GART_REGS(gart);
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spin_unlock_irqrestore(&gart->pte_lock, flags);
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return 0;
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}
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static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
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size_t bytes)
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{
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struct gart_device *gart = domain->priv;
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unsigned long flags;
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if (!gart_iova_range_valid(gart, iova, bytes))
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return 0;
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spin_lock_irqsave(&gart->pte_lock, flags);
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gart_set_pte(gart, iova, 0);
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FLUSH_GART_REGS(gart);
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spin_unlock_irqrestore(&gart->pte_lock, flags);
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return 0;
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}
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static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
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unsigned long iova)
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{
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struct gart_device *gart = domain->priv;
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unsigned long pte;
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phys_addr_t pa;
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unsigned long flags;
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if (!gart_iova_range_valid(gart, iova, 0))
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return -EINVAL;
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spin_lock_irqsave(&gart->pte_lock, flags);
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pte = gart_read_pte(gart, iova);
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spin_unlock_irqrestore(&gart->pte_lock, flags);
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pa = (pte & GART_PAGE_MASK);
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if (!pfn_valid(__phys_to_pfn(pa))) {
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dev_err(gart->dev, "No entry for %08lx:%08x\n", iova, pa);
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gart_dump_table(gart);
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return -EINVAL;
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}
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return pa;
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}
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static int gart_iommu_domain_has_cap(struct iommu_domain *domain,
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unsigned long cap)
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{
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return 0;
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}
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static struct iommu_ops gart_iommu_ops = {
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.domain_init = gart_iommu_domain_init,
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.domain_destroy = gart_iommu_domain_destroy,
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.attach_dev = gart_iommu_attach_dev,
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.detach_dev = gart_iommu_detach_dev,
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.map = gart_iommu_map,
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.unmap = gart_iommu_unmap,
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.iova_to_phys = gart_iommu_iova_to_phys,
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.domain_has_cap = gart_iommu_domain_has_cap,
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.pgsize_bitmap = GART_IOMMU_PGSIZES,
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};
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static int tegra_gart_suspend(struct device *dev)
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{
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struct gart_device *gart = dev_get_drvdata(dev);
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unsigned long iova;
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u32 *data = gart->savedata;
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unsigned long flags;
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spin_lock_irqsave(&gart->pte_lock, flags);
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for_each_gart_pte(gart, iova)
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*(data++) = gart_read_pte(gart, iova);
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spin_unlock_irqrestore(&gart->pte_lock, flags);
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return 0;
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}
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static int tegra_gart_resume(struct device *dev)
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{
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struct gart_device *gart = dev_get_drvdata(dev);
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unsigned long flags;
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spin_lock_irqsave(&gart->pte_lock, flags);
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do_gart_setup(gart, gart->savedata);
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spin_unlock_irqrestore(&gart->pte_lock, flags);
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return 0;
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}
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static int tegra_gart_probe(struct platform_device *pdev)
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{
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struct gart_device *gart;
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struct resource *res, *res_remap;
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void __iomem *gart_regs;
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int err;
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struct device *dev = &pdev->dev;
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if (gart_handle)
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return -EIO;
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BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
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/* the GART memory aperture is required */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res || !res_remap) {
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dev_err(dev, "GART memory aperture expected\n");
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return -ENXIO;
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}
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gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL);
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if (!gart) {
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dev_err(dev, "failed to allocate gart_device\n");
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return -ENOMEM;
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}
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gart_regs = devm_ioremap(dev, res->start, resource_size(res));
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if (!gart_regs) {
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dev_err(dev, "failed to remap GART registers\n");
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err = -ENXIO;
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goto fail;
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}
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gart->dev = &pdev->dev;
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spin_lock_init(&gart->pte_lock);
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spin_lock_init(&gart->client_lock);
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INIT_LIST_HEAD(&gart->client);
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gart->regs = gart_regs;
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gart->iovmm_base = (dma_addr_t)res_remap->start;
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gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT);
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gart->savedata = vmalloc(sizeof(u32) * gart->page_count);
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if (!gart->savedata) {
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dev_err(dev, "failed to allocate context save area\n");
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err = -ENOMEM;
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goto fail;
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}
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platform_set_drvdata(pdev, gart);
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do_gart_setup(gart, NULL);
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gart_handle = gart;
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return 0;
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fail:
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if (gart_regs)
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devm_iounmap(dev, gart_regs);
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if (gart && gart->savedata)
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vfree(gart->savedata);
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devm_kfree(dev, gart);
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return err;
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}
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static int tegra_gart_remove(struct platform_device *pdev)
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{
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struct gart_device *gart = platform_get_drvdata(pdev);
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struct device *dev = gart->dev;
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writel(0, gart->regs + GART_CONFIG);
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if (gart->savedata)
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vfree(gart->savedata);
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if (gart->regs)
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devm_iounmap(dev, gart->regs);
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devm_kfree(dev, gart);
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gart_handle = NULL;
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return 0;
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}
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const struct dev_pm_ops tegra_gart_pm_ops = {
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.suspend = tegra_gart_suspend,
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.resume = tegra_gart_resume,
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};
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static struct platform_driver tegra_gart_driver = {
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.probe = tegra_gart_probe,
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.remove = tegra_gart_remove,
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.driver = {
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.owner = THIS_MODULE,
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.name = "tegra-gart",
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.pm = &tegra_gart_pm_ops,
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},
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};
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static int __devinit tegra_gart_init(void)
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{
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bus_set_iommu(&platform_bus_type, &gart_iommu_ops);
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return platform_driver_register(&tegra_gart_driver);
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}
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static void __exit tegra_gart_exit(void)
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{
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platform_driver_unregister(&tegra_gart_driver);
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}
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|
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subsys_initcall(tegra_gart_init);
|
||||
module_exit(tegra_gart_exit);
|
||||
|
||||
MODULE_DESCRIPTION("IOMMU API for GART in Tegra20");
|
||||
MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue