pinctrl: cs42l43: Add support for the cs42l43
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface (Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed for portable applications. It provides a high dynamic range, stereo DAC for headphone output, two integrated Class D amplifiers for loudspeakers, and two ADCs for wired headset microphone input or stereo line input. PDM inputs are provided for digital microphones. Add a basic pinctrl driver which supports driver strength for the various pins, gpios, and pinmux for the 2 multi-function pins. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230804104602.395892-5-ckeepax@opensource.cirrus.com Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Charles Keepax
Lee Jones
parent
ace6d14481
commit
d5282a5392
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@ -4880,6 +4880,7 @@ L: patches@opensource.cirrus.com
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S: Maintained
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F: Documentation/devicetree/bindings/sound/cirrus,cs*
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F: drivers/mfd/cs42l43*
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F: drivers/pinctrl/cirrus/pinctrl-cs42l43*
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F: include/dt-bindings/sound/cs*
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F: include/linux/mfd/cs42l43*
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F: include/sound/cs*
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@ -1,4 +1,15 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config PINCTRL_CS42L43
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tristate "Cirrus Logic CS42L43 Pinctrl Driver"
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depends on MFD_CS42L43
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select GPIOLIB
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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help
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Select this to support the GPIO/Pinctrl functions of the Cirrus
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Logic CS42L43 PC CODEC.
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config PINCTRL_LOCHNAGAR
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tristate "Cirrus Logic Lochnagar pinctrl driver"
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depends on MFD_LOCHNAGAR
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@ -1,5 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# Cirrus Logic pinctrl drivers
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obj-$(CONFIG_PINCTRL_CS42L43) += pinctrl-cs42l43.o
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obj-$(CONFIG_PINCTRL_LOCHNAGAR) += pinctrl-lochnagar.o
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pinctrl-madera-objs := pinctrl-madera-core.o
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@ -0,0 +1,609 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// CS42L43 Pinctrl and GPIO driver
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//
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// Copyright (c) 2023 Cirrus Logic, Inc. and
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// Cirrus Logic International Semiconductor Ltd.
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#include <linux/bits.h>
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#include <linux/build_bug.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/mfd/cs42l43.h>
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#include <linux/mfd/cs42l43-regs.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/string_helpers.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include "../pinctrl-utils.h"
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#define CS42L43_NUM_GPIOS 3
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struct cs42l43_pin {
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struct gpio_chip gpio_chip;
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struct device *dev;
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struct regmap *regmap;
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bool shutters_locked;
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};
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struct cs42l43_pin_data {
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unsigned int reg;
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unsigned int shift;
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unsigned int mask;
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};
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#define CS42L43_PIN(_number, _name, _reg, _field) { \
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.number = _number, .name = _name, \
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.drv_data = &((struct cs42l43_pin_data){ \
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.reg = CS42L43_##_reg, \
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.shift = CS42L43_##_field##_DRV_SHIFT, \
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.mask = CS42L43_##_field##_DRV_MASK, \
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}), \
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}
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static const struct pinctrl_pin_desc cs42l43_pin_pins[] = {
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CS42L43_PIN(0, "gpio1", DRV_CTRL4, GPIO1),
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CS42L43_PIN(1, "gpio2", DRV_CTRL4, GPIO2),
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CS42L43_PIN(2, "gpio3", DRV_CTRL4, GPIO3),
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CS42L43_PIN(3, "asp_dout", DRV_CTRL1, ASP_DOUT),
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CS42L43_PIN(4, "asp_fsync", DRV_CTRL1, ASP_FSYNC),
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CS42L43_PIN(5, "asp_bclk", DRV_CTRL1, ASP_BCLK),
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CS42L43_PIN(6, "pdmout2_clk", DRV_CTRL3, PDMOUT2_CLK),
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CS42L43_PIN(7, "pdmout2_data", DRV_CTRL3, PDMOUT2_DATA),
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CS42L43_PIN(8, "pdmout1_clk", DRV_CTRL3, PDMOUT1_CLK),
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CS42L43_PIN(9, "pdmout1_data", DRV_CTRL3, PDMOUT1_DATA),
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CS42L43_PIN(10, "i2c_sda", DRV_CTRL3, I2C_SDA),
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CS42L43_PIN(11, "i2c_scl", DRV_CTRL_5, I2C_SCL),
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CS42L43_PIN(12, "spi_miso", DRV_CTRL3, SPI_MISO),
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CS42L43_PIN(13, "spi_sck", DRV_CTRL_5, SPI_SCK),
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CS42L43_PIN(14, "spi_ssb", DRV_CTRL_5, SPI_SSB),
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};
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static const unsigned int cs42l43_pin_gpio1_pins[] = { 0 };
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static const unsigned int cs42l43_pin_gpio2_pins[] = { 1 };
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static const unsigned int cs42l43_pin_gpio3_pins[] = { 2 };
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static const unsigned int cs42l43_pin_asp_pins[] = { 3, 4, 5 };
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static const unsigned int cs42l43_pin_pdmout2_pins[] = { 6, 7 };
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static const unsigned int cs42l43_pin_pdmout1_pins[] = { 8, 9 };
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static const unsigned int cs42l43_pin_i2c_pins[] = { 10, 11 };
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static const unsigned int cs42l43_pin_spi_pins[] = { 12, 13, 14 };
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#define CS42L43_PINGROUP(_name) \
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PINCTRL_PINGROUP(#_name, cs42l43_pin_##_name##_pins, \
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ARRAY_SIZE(cs42l43_pin_##_name##_pins))
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static const struct pingroup cs42l43_pin_groups[] = {
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CS42L43_PINGROUP(gpio1),
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CS42L43_PINGROUP(gpio2),
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CS42L43_PINGROUP(gpio3),
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CS42L43_PINGROUP(asp),
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CS42L43_PINGROUP(pdmout2),
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CS42L43_PINGROUP(pdmout1),
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CS42L43_PINGROUP(i2c),
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CS42L43_PINGROUP(spi),
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};
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static int cs42l43_pin_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(cs42l43_pin_groups);
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}
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static const char *cs42l43_pin_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group_idx)
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{
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return cs42l43_pin_groups[group_idx].name;
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}
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static int cs42l43_pin_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int group_idx,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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*pins = cs42l43_pin_groups[group_idx].pins;
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*num_pins = cs42l43_pin_groups[group_idx].npins;
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return 0;
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}
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static const struct pinctrl_ops cs42l43_pin_group_ops = {
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.get_groups_count = cs42l43_pin_get_groups_count,
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.get_group_name = cs42l43_pin_get_group_name,
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.get_group_pins = cs42l43_pin_get_group_pins,
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#if IS_ENABLED(CONFIG_OF)
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinconf_generic_dt_free_map,
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#endif
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};
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enum cs42l43_pin_funcs {
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CS42L43_FUNC_GPIO,
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CS42L43_FUNC_SPDIF,
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CS42L43_FUNC_IRQ,
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CS42L43_FUNC_MIC_SHT,
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CS42L43_FUNC_SPK_SHT,
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CS42L43_FUNC_MAX
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};
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static const char * const cs42l43_pin_funcs[] = {
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"gpio", "spdif", "irq", "mic-shutter", "spk-shutter",
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};
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static const char * const cs42l43_pin_gpio_groups[] = { "gpio1", "gpio3" };
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static const char * const cs42l43_pin_spdif_groups[] = { "gpio3" };
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static const char * const cs42l43_pin_irq_groups[] = { "gpio1" };
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static const char * const cs42l43_pin_shutter_groups[] = { "gpio1", "gpio2", "gpio3" };
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static const struct pinfunction cs42l43_pin_func_groups[] = {
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PINCTRL_PINFUNCTION("gpio", cs42l43_pin_gpio_groups,
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ARRAY_SIZE(cs42l43_pin_gpio_groups)),
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PINCTRL_PINFUNCTION("spdif", cs42l43_pin_spdif_groups,
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ARRAY_SIZE(cs42l43_pin_spdif_groups)),
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PINCTRL_PINFUNCTION("irq", cs42l43_pin_irq_groups,
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ARRAY_SIZE(cs42l43_pin_irq_groups)),
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PINCTRL_PINFUNCTION("mic-shutter", cs42l43_pin_shutter_groups,
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ARRAY_SIZE(cs42l43_pin_shutter_groups)),
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PINCTRL_PINFUNCTION("spk-shutter", cs42l43_pin_shutter_groups,
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ARRAY_SIZE(cs42l43_pin_shutter_groups)),
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};
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static_assert(ARRAY_SIZE(cs42l43_pin_funcs) == CS42L43_FUNC_MAX);
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static_assert(ARRAY_SIZE(cs42l43_pin_func_groups) == CS42L43_FUNC_MAX);
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static int cs42l43_pin_get_func_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(cs42l43_pin_funcs);
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}
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static const char *cs42l43_pin_get_func_name(struct pinctrl_dev *pctldev,
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unsigned int func_idx)
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{
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return cs42l43_pin_funcs[func_idx];
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}
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static int cs42l43_pin_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned int func_idx,
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const char * const **groups,
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unsigned int * const num_groups)
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{
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*groups = cs42l43_pin_func_groups[func_idx].groups;
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*num_groups = cs42l43_pin_func_groups[func_idx].ngroups;
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return 0;
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}
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static int cs42l43_pin_set_mux(struct pinctrl_dev *pctldev,
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unsigned int func_idx, unsigned int group_idx)
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{
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struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
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unsigned int reg, mask, val;
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dev_dbg(priv->dev, "Setting %s to %s\n",
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cs42l43_pin_groups[group_idx].name, cs42l43_pin_funcs[func_idx]);
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switch (func_idx) {
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case CS42L43_FUNC_MIC_SHT:
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reg = CS42L43_SHUTTER_CONTROL;
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mask = CS42L43_MIC_SHUTTER_CFG_MASK;
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val = 0x2 << (group_idx + CS42L43_MIC_SHUTTER_CFG_SHIFT);
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break;
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case CS42L43_FUNC_SPK_SHT:
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reg = CS42L43_SHUTTER_CONTROL;
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mask = CS42L43_SPK_SHUTTER_CFG_MASK;
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val = 0x2 << (group_idx + CS42L43_SPK_SHUTTER_CFG_SHIFT);
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break;
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default:
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reg = CS42L43_GPIO_FN_SEL;
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mask = BIT(group_idx + CS42L43_GPIO1_FN_SEL_SHIFT);
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val = (func_idx == CS42L43_FUNC_GPIO) ?
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(0x1 << (group_idx + CS42L43_GPIO1_FN_SEL_SHIFT)) : 0;
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break;
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}
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if (priv->shutters_locked && reg == CS42L43_SHUTTER_CONTROL) {
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dev_err(priv->dev, "Shutter configuration not available\n");
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return -EPERM;
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}
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return regmap_update_bits(priv->regmap, reg, mask, val);
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}
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static int cs42l43_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset, bool input)
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{
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struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
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unsigned int shift = offset + CS42L43_GPIO1_DIR_SHIFT;
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int ret;
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dev_dbg(priv->dev, "Setting gpio%d to %s\n",
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offset + 1, input ? "input" : "output");
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ret = pm_runtime_resume_and_get(priv->dev);
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if (ret) {
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dev_err(priv->dev, "Failed to resume for direction: %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,
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BIT(shift), !!input << shift);
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if (ret)
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dev_err(priv->dev, "Failed to set gpio%d direction: %d\n",
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offset + 1, ret);
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pm_runtime_put(priv->dev);
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return ret;
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}
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static int cs42l43_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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return cs42l43_pin_set_mux(pctldev, 0, offset);
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}
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static void cs42l43_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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cs42l43_gpio_set_direction(pctldev, range, offset, true);
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}
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static const struct pinmux_ops cs42l43_pin_mux_ops = {
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.get_functions_count = cs42l43_pin_get_func_count,
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.get_function_name = cs42l43_pin_get_func_name,
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.get_function_groups = cs42l43_pin_get_func_groups,
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.set_mux = cs42l43_pin_set_mux,
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.gpio_request_enable = cs42l43_gpio_request_enable,
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.gpio_disable_free = cs42l43_gpio_disable_free,
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.gpio_set_direction = cs42l43_gpio_set_direction,
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.strict = true,
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};
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static const unsigned int cs42l43_pin_drv_str_ma[] = { 1, 2, 4, 8, 9, 10, 12, 16 };
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static inline int cs42l43_pin_get_drv_str(struct cs42l43_pin *priv, unsigned int pin)
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{
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const struct cs42l43_pin_data *pdat = cs42l43_pin_pins[pin].drv_data;
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unsigned int val;
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int ret;
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ret = regmap_read(priv->regmap, pdat->reg, &val);
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if (ret)
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return ret;
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return cs42l43_pin_drv_str_ma[(val & pdat->mask) >> pdat->shift];
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}
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static inline int cs42l43_pin_set_drv_str(struct cs42l43_pin *priv, unsigned int pin,
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unsigned int ma)
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{
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const struct cs42l43_pin_data *pdat = cs42l43_pin_pins[pin].drv_data;
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int i;
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for (i = 0; i < ARRAY_SIZE(cs42l43_pin_drv_str_ma); i++) {
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if (ma == cs42l43_pin_drv_str_ma[i]) {
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if ((i << pdat->shift) > pdat->mask)
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goto err;
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dev_dbg(priv->dev, "Set drive strength for %s to %d mA\n",
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cs42l43_pin_pins[pin].name, ma);
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return regmap_update_bits(priv->regmap, pdat->reg,
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pdat->mask, i << pdat->shift);
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}
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}
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err:
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dev_err(priv->dev, "Invalid drive strength for %s: %d mA\n",
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cs42l43_pin_pins[pin].name, ma);
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return -EINVAL;
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}
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static inline int cs42l43_pin_get_db(struct cs42l43_pin *priv, unsigned int pin)
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{
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unsigned int val;
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int ret;
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if (pin >= CS42L43_NUM_GPIOS)
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return -ENOTSUPP;
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ret = regmap_read(priv->regmap, CS42L43_GPIO_CTRL2, &val);
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if (ret)
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return ret;
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if (val & (CS42L43_GPIO1_DEGLITCH_BYP_MASK << pin))
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return 0;
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return 85; // Debounce is roughly 85uS
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}
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static inline int cs42l43_pin_set_db(struct cs42l43_pin *priv, unsigned int pin,
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unsigned int us)
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{
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if (pin >= CS42L43_NUM_GPIOS)
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return -ENOTSUPP;
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dev_dbg(priv->dev, "Set debounce %s for %s\n",
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str_on_off(us), cs42l43_pin_pins[pin].name);
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return regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL2,
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CS42L43_GPIO1_DEGLITCH_BYP_MASK << pin,
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!!us << pin);
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}
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static int cs42l43_pin_config_get(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *config)
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{
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struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
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unsigned int param = pinconf_to_config_param(*config);
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int ret;
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switch (param) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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ret = cs42l43_pin_get_drv_str(priv, pin);
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if (ret < 0)
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return ret;
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break;
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case PIN_CONFIG_INPUT_DEBOUNCE:
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ret = cs42l43_pin_get_db(priv, pin);
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if (ret < 0)
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||||
return ret;
|
||||
break;
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
*config = pinconf_to_config_packed(param, ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l43_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
unsigned long *configs, unsigned int num_configs)
|
||||
{
|
||||
struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
while (num_configs) {
|
||||
val = pinconf_to_config_argument(*configs);
|
||||
|
||||
switch (pinconf_to_config_param(*configs)) {
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
ret = cs42l43_pin_set_drv_str(priv, pin, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case PIN_CONFIG_INPUT_DEBOUNCE:
|
||||
ret = cs42l43_pin_set_db(priv, pin, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
configs++;
|
||||
num_configs--;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l43_pin_config_group_get(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector, unsigned long *config)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < cs42l43_pin_groups[selector].npins; ++i) {
|
||||
ret = cs42l43_pin_config_get(pctldev,
|
||||
cs42l43_pin_groups[selector].pins[i],
|
||||
config);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cs42l43_pin_config_group_set(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector,
|
||||
unsigned long *configs,
|
||||
unsigned int num_configs)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < cs42l43_pin_groups[selector].npins; ++i) {
|
||||
ret = cs42l43_pin_config_set(pctldev,
|
||||
cs42l43_pin_groups[selector].pins[i],
|
||||
configs, num_configs);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinconf_ops cs42l43_pin_conf_ops = {
|
||||
.is_generic = true,
|
||||
|
||||
.pin_config_get = cs42l43_pin_config_get,
|
||||
.pin_config_set = cs42l43_pin_config_set,
|
||||
.pin_config_group_get = cs42l43_pin_config_group_get,
|
||||
.pin_config_group_set = cs42l43_pin_config_group_set,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc cs42l43_pin_desc = {
|
||||
.name = "cs42l43-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
|
||||
.pins = cs42l43_pin_pins,
|
||||
.npins = ARRAY_SIZE(cs42l43_pin_pins),
|
||||
|
||||
.pctlops = &cs42l43_pin_group_ops,
|
||||
.pmxops = &cs42l43_pin_mux_ops,
|
||||
.confops = &cs42l43_pin_conf_ops,
|
||||
};
|
||||
|
||||
static int cs42l43_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct cs42l43_pin *priv = gpiochip_get_data(chip);
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(priv->dev);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "Failed to resume for get: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_read(priv->regmap, CS42L43_GPIO_STS, &val);
|
||||
if (ret)
|
||||
dev_err(priv->dev, "Failed to get gpio%d: %d\n", offset + 1, ret);
|
||||
else
|
||||
ret = !!(val & BIT(offset + CS42L43_GPIO1_STS_SHIFT));
|
||||
|
||||
pm_runtime_put(priv->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
struct cs42l43_pin *priv = gpiochip_get_data(chip);
|
||||
unsigned int shift = offset + CS42L43_GPIO1_LVL_SHIFT;
|
||||
int ret;
|
||||
|
||||
dev_dbg(priv->dev, "Setting gpio%d to %s\n",
|
||||
offset + 1, value ? "high" : "low");
|
||||
|
||||
ret = pm_runtime_resume_and_get(priv->dev);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "Failed to resume for set: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,
|
||||
BIT(shift), value << shift);
|
||||
if (ret)
|
||||
dev_err(priv->dev, "Failed to set gpio%d: %d\n", offset + 1, ret);
|
||||
|
||||
pm_runtime_put(priv->dev);
|
||||
}
|
||||
|
||||
static int cs42l43_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
return pinctrl_gpio_direction_input(chip->base + offset);
|
||||
}
|
||||
|
||||
static int cs42l43_gpio_direction_out(struct gpio_chip *chip,
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
cs42l43_gpio_set(chip, offset, value);
|
||||
|
||||
return pinctrl_gpio_direction_output(chip->base + offset);
|
||||
}
|
||||
|
||||
static int cs42l43_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
{
|
||||
struct cs42l43_pin *priv = gpiochip_get_data(chip);
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_add_pin_range(&priv->gpio_chip, priv->gpio_chip.label,
|
||||
0, 0, CS42L43_NUM_GPIOS);
|
||||
if (ret)
|
||||
dev_err(priv->dev, "Failed to add GPIO pin range: %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cs42l43_pin_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
|
||||
struct cs42l43_pin *priv;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = &pdev->dev;
|
||||
priv->regmap = cs42l43->regmap;
|
||||
|
||||
priv->shutters_locked = cs42l43->hw_lock;
|
||||
|
||||
priv->gpio_chip.request = gpiochip_generic_request;
|
||||
priv->gpio_chip.free = gpiochip_generic_free;
|
||||
priv->gpio_chip.direction_input = cs42l43_gpio_direction_in;
|
||||
priv->gpio_chip.direction_output = cs42l43_gpio_direction_out;
|
||||
priv->gpio_chip.add_pin_ranges = cs42l43_gpio_add_pin_ranges;
|
||||
priv->gpio_chip.get = cs42l43_gpio_get;
|
||||
priv->gpio_chip.set = cs42l43_gpio_set;
|
||||
priv->gpio_chip.label = dev_name(priv->dev);
|
||||
priv->gpio_chip.parent = priv->dev;
|
||||
priv->gpio_chip.can_sleep = true;
|
||||
priv->gpio_chip.base = -1;
|
||||
priv->gpio_chip.ngpio = CS42L43_NUM_GPIOS;
|
||||
|
||||
if (is_of_node(fwnode)) {
|
||||
fwnode = fwnode_get_named_child_node(fwnode, "pinctrl");
|
||||
|
||||
if (fwnode && !fwnode->dev)
|
||||
fwnode->dev = priv->dev;
|
||||
}
|
||||
|
||||
priv->gpio_chip.fwnode = fwnode;
|
||||
|
||||
device_set_node(priv->dev, fwnode);
|
||||
|
||||
devm_pm_runtime_enable(priv->dev);
|
||||
pm_runtime_idle(priv->dev);
|
||||
|
||||
pctldev = devm_pinctrl_register(priv->dev, &cs42l43_pin_desc, priv);
|
||||
if (IS_ERR(pctldev))
|
||||
return dev_err_probe(priv->dev, PTR_ERR(pctldev),
|
||||
"Failed to register pinctrl\n");
|
||||
|
||||
ret = devm_gpiochip_add_data(priv->dev, &priv->gpio_chip, priv);
|
||||
if (ret)
|
||||
return dev_err_probe(priv->dev, ret,
|
||||
"Failed to register gpiochip\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_device_id cs42l43_pin_id_table[] = {
|
||||
{ "cs42l43-pinctrl", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, cs42l43_pin_id_table);
|
||||
|
||||
static struct platform_driver cs42l43_pin_driver = {
|
||||
.driver = {
|
||||
.name = "cs42l43-pinctrl",
|
||||
},
|
||||
.probe = cs42l43_pin_probe,
|
||||
.id_table = cs42l43_pin_id_table,
|
||||
};
|
||||
module_platform_driver(cs42l43_pin_driver);
|
||||
|
||||
MODULE_DESCRIPTION("CS42L43 Pinctrl Driver");
|
||||
MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue