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powerpc/fsl-booke: Work around erratum A-006958 

Erratum A-006598 says that 64-bit mftb is not atomic -- it's subject
to a similar race condition as doing mftbu/mftbl on 32-bit.  The lower
half of timebase is updated before the upper half; thus, we can share
the workaround for a similar bug on Cell.  This workaround involves
looping if the lower half of timebase is zero, thus avoiding the need
for a scratch register (other than CR0).  This workaround must be
avoided when the timebase is frozen, such as during the timebase sync
code.

This deals with kernel and vdso accesses, but other userspace accesses
will of course need to be fixed elsewhere.

Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2013-07-23 20:21:11 -05:00
parent afbcdd97bf
commit d52459ca30
4 changed files with 32 additions and 4 deletions
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9
arch/powerpc/include/asm/cputable.h
View File

@ -371,14 +371,19 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
/*
* e5500/e6500 erratum A-006958 is a timebase bug that can use the
* same workaround as CPU_FTR_CELL_TB_BUG.
*/
#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_CELL_TB_BUG)
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */

2
arch/powerpc/include/asm/ppc_asm.h
View File

@ -431,7 +431,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
#define ISYNC_601
#endif
#ifdef CONFIG_PPC_CELL
#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
#define MFTB(dest) \
90: mftb dest; \
BEGIN_FTR_SECTION_NESTED(96); \

2
arch/powerpc/include/asm/reg.h
View File

@ -1117,7 +1117,7 @@
: "memory")
#ifdef __powerpc64__
#ifdef CONFIG_PPC_CELL
#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
#define mftb() ({unsigned long rval; \
asm volatile( \
"90: mftb %0;\n" \

23
arch/powerpc/platforms/85xx/smp.c
View File

@ -69,7 +69,30 @@ static void mpc85xx_give_timebase(void)
tb_req = 0;
mpc85xx_timebase_freeze(1);
#ifdef CONFIG_PPC64
/*
* e5500/e6500 have a workaround for erratum A-006958 in place
* that will reread the timebase until TBL is non-zero.
* That would be a bad thing when the timebase is frozen.
*
* Thus, we read it manually, and instead of checking that
* TBL is non-zero, we ensure that TB does not change. We don't
* do that for the main mftb implementation, because it requires
* a scratch register
*/
{
u64 prev;
asm volatile("mftb %0" : "=r" (timebase));
do {
prev = timebase;
asm volatile("mftb %0" : "=r" (timebase));
} while (prev != timebase);
}
#else
timebase = get_tb();
#endif
mb();
tb_valid = 1;