drm/nouveau/gr/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
6e1f34e33c
commit
d521097f58
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@ -155,6 +155,8 @@
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#define PASCAL_A /* cl9097.h */ 0x0000c097
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#define PASCAL_B /* cl9097.h */ 0x0000c197
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#define VOLTA_A /* cl9097.h */ 0x0000c397
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#define NV74_BSP 0x000074b0
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#define GT212_MSVLD 0x000085b1
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@ -194,6 +196,7 @@
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#define MAXWELL_COMPUTE_B 0x0000b1c0
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#define PASCAL_COMPUTE_A 0x0000c0c0
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#define PASCAL_COMPUTE_B 0x0000c1c0
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#define VOLTA_COMPUTE_A 0x0000c3c0
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#define NV74_CIPHER 0x000074c1
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#endif
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@ -48,4 +48,5 @@ int gp102_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
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int gp104_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
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int gp107_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
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int gp10b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
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int gv100_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
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#endif
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@ -2413,6 +2413,7 @@ nv140_chipset = {
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.mmu = gv100_mmu_new,
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.pci = gp100_pci_new,
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.pmu = gp102_pmu_new,
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.secboot = gp108_secboot_new,
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.therm = gp100_therm_new,
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.timer = gk20a_timer_new,
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.top = gk104_top_new,
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@ -2428,6 +2429,9 @@ nv140_chipset = {
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.ce[8] = gv100_ce_new,
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.dma = gv100_dma_new,
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.fifo = gv100_fifo_new,
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.gr = gv100_gr_new,
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.nvdec = gp102_nvdec_new,
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.sec2 = gp102_sec2_new,
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};
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static int
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@ -36,6 +36,7 @@ nvkm-y += nvkm/engine/gr/gp102.o
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nvkm-y += nvkm/engine/gr/gp104.o
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nvkm-y += nvkm/engine/gr/gp107.o
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nvkm-y += nvkm/engine/gr/gp10b.o
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nvkm-y += nvkm/engine/gr/gv100.o
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nvkm-y += nvkm/engine/gr/ctxnv40.o
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nvkm-y += nvkm/engine/gr/ctxnv50.o
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@ -57,3 +58,4 @@ nvkm-y += nvkm/engine/gr/ctxgp100.o
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nvkm-y += nvkm/engine/gr/ctxgp102.o
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nvkm-y += nvkm/engine/gr/ctxgp104.o
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nvkm-y += nvkm/engine/gr/ctxgp107.o
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nvkm-y += nvkm/engine/gr/ctxgv100.o
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@ -1396,10 +1396,14 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
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gf100_grctx_generate_floorsweep(gr);
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if (grctx->r400088) grctx->r400088(gr, false);
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if (gr->fuc_bundle)
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gf100_gr_icmd(gr, gr->fuc_bundle);
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else
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gf100_gr_icmd(gr, grctx->icmd);
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if (grctx->sw_veid_bundle_init)
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gf100_gr_icmd(gr, grctx->sw_veid_bundle_init);
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if (grctx->r400088) grctx->r400088(gr, true);
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nvkm_wr32(device, 0x404154, idle_timeout);
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@ -1448,6 +1452,9 @@ gf100_grctx_generate(struct gf100_gr *gr)
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break;
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);
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if (grctx->unkn88c)
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grctx->unkn88c(gr, true);
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/* Reset FECS. */
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nvkm_wr32(device, 0x409614, 0x00000070);
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nvkm_usec(device, 10, NVKM_DELAY);
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@ -1455,6 +1462,9 @@ gf100_grctx_generate(struct gf100_gr *gr)
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nvkm_usec(device, 10, NVKM_DELAY);
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nvkm_rd32(device, 0x409614);
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if (grctx->unkn88c)
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grctx->unkn88c(gr, false);
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/* NV_PGRAPH_FE_PWR_MODE_AUTO. */
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nvkm_wr32(device, 0x404170, 0x00000010);
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@ -21,6 +21,7 @@ void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int)
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#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
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struct gf100_grctx_func {
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void (*unkn88c)(struct gf100_gr *, bool on);
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/* main context generation function */
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void (*main)(struct gf100_gr *, struct gf100_grctx *);
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/* context-specific modify-on-first-load list generation function */
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@ -35,6 +36,7 @@ struct gf100_grctx_func {
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/* indirect context data, generated with icmds/mthds */
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const struct gf100_gr_pack *icmd;
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const struct gf100_gr_pack *mthd;
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const struct gf100_gr_pack *sw_veid_bundle_init;
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/* bundle circular buffer */
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void (*bundle)(struct gf100_grctx *);
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u32 bundle_size;
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@ -66,6 +68,7 @@ struct gf100_grctx_func {
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void (*tpc_mask)(struct gf100_gr *);
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void (*smid_config)(struct gf100_gr *);
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/* misc other things */
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void (*r400088)(struct gf100_gr *, bool);
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void (*r419cb8)(struct gf100_gr *);
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void (*r418800)(struct gf100_gr *);
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void (*r419eb0)(struct gf100_gr *);
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@ -148,6 +151,8 @@ extern const struct gf100_grctx_func gp104_grctx;
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extern const struct gf100_grctx_func gp107_grctx;
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extern const struct gf100_grctx_func gv100_grctx;
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/* context init value lists */
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extern const struct gf100_gr_pack gf100_grctx_pack_icmd[];
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@ -0,0 +1,215 @@
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/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "ctxgf100.h"
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/*******************************************************************************
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* PGRAPH context implementation
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******************************************************************************/
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static const struct gf100_gr_init
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gv100_grctx_init_sw_veid_bundle_init_0[] = {
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{ 0x00001000, 64, 0x00100000, 0x00000008 },
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{ 0x00000941, 64, 0x00100000, 0x00000000 },
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{ 0x0000097e, 64, 0x00100000, 0x00000000 },
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{ 0x0000097f, 64, 0x00100000, 0x00000100 },
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{ 0x0000035c, 64, 0x00100000, 0x00000000 },
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{ 0x0000035d, 64, 0x00100000, 0x00000000 },
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{ 0x00000a08, 64, 0x00100000, 0x00000000 },
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{ 0x00000a09, 64, 0x00100000, 0x00000000 },
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{ 0x00000a0a, 64, 0x00100000, 0x00000000 },
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{ 0x00000352, 64, 0x00100000, 0x00000000 },
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{ 0x00000353, 64, 0x00100000, 0x00000000 },
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{ 0x00000358, 64, 0x00100000, 0x00000000 },
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{ 0x00000359, 64, 0x00100000, 0x00000000 },
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{ 0x00000370, 64, 0x00100000, 0x00000000 },
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{ 0x00000371, 64, 0x00100000, 0x00000000 },
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{ 0x00000372, 64, 0x00100000, 0x000fffff },
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{ 0x00000366, 64, 0x00100000, 0x00000000 },
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{ 0x00000367, 64, 0x00100000, 0x00000000 },
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{ 0x00000368, 64, 0x00100000, 0x00000fff },
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{ 0x00000623, 64, 0x00100000, 0x00000000 },
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{ 0x00000624, 64, 0x00100000, 0x00000000 },
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{ 0x0001e100, 1, 0x00000001, 0x02000001 },
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{}
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};
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static const struct gf100_gr_pack
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gv100_grctx_pack_sw_veid_bundle_init[] = {
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{ gv100_grctx_init_sw_veid_bundle_init_0 },
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{}
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};
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static void
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gv100_grctx_generate_attrib(struct gf100_grctx *info)
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{
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struct gf100_gr *gr = info->gr;
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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const u32 alpha = grctx->alpha_nr;
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const u32 attrib = grctx->attrib_nr;
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const u32 gfxp = grctx->gfxp_nr;
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const int s = 12;
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const int max_batches = 0xffff;
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u32 size = grctx->alpha_nr_max * gr->tpc_total;
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u32 ao = 0;
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u32 bo = ao + size;
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int gpc, ppc, b, n = 0;
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size += grctx->gfxp_nr * gr->tpc_total;
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size = ((size * 0x20) + 128) & ~127;
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b = mmio_vram(info, size, (1 << s), false);
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mmio_refn(info, 0x418810, 0x80000000, s, b);
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mmio_refn(info, 0x419848, 0x10000000, s, b);
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mmio_refn(info, 0x419c2c, 0x10000000, s, b);
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mmio_refn(info, 0x419e00, 0x00000000, s, b);
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mmio_wr32(info, 0x419e04, 0x80000000 | size >> 7);
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mmio_wr32(info, 0x405830, attrib);
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mmio_wr32(info, 0x40585c, alpha);
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mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
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const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
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const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
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const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc];
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const u32 u = 0x418ea0 + (n * 0x04);
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const u32 o = PPC_UNIT(gpc, ppc, 0);
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if (!(gr->ppc_mask[gpc] & (1 << ppc)))
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continue;
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mmio_wr32(info, o + 0xc0, gs);
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mmio_wr32(info, o + 0xf4, bo);
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mmio_wr32(info, o + 0xf0, bs);
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bo += gs;
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mmio_wr32(info, o + 0xe4, as);
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mmio_wr32(info, o + 0xf8, ao);
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ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
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mmio_wr32(info, u, bs);
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}
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}
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mmio_wr32(info, 0x4181e4, 0x00000100);
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mmio_wr32(info, 0x41befc, 0x00000100);
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}
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static void
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gv100_grctx_generate_rop_mapping(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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u32 data;
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int i, j;
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/* Pack tile map into register format. */
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nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
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gr->screen_tile_row_offset);
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for (i = 0; i < 11; i++) {
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for (data = 0, j = 0; j < 6; j++)
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data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);
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nvkm_wr32(device, 0x418b08 + (i * 4), data);
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nvkm_wr32(device, 0x41bf00 + (i * 4), data);
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nvkm_wr32(device, 0x40780c + (i * 4), data);
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}
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/* GPC_BROADCAST.TP_BROADCAST */
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nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
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gr->screen_tile_row_offset);
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for (i = 0, j = 1; i < 5; i++, j += 4) {
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u8 v19 = (1 << (j + 0)) % gr->tpc_total;
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u8 v20 = (1 << (j + 1)) % gr->tpc_total;
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u8 v21 = (1 << (j + 2)) % gr->tpc_total;
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u8 v22 = (1 << (j + 3)) % gr->tpc_total;
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nvkm_wr32(device, 0x41bfb0 + (i * 4), (v22 << 24) |
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(v21 << 16) |
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(v20 << 8) |
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v19);
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}
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/* UNK78xx */
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nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
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gr->screen_tile_row_offset);
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}
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static void
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gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000);
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}
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static void
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gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
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nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
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}
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static void
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gv100_grctx_generate_unkn(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
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nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
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nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
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nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
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nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
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}
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static void
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gv100_grctx_unkn88c(struct gf100_gr *gr, bool on)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const u32 mask = 0x00000010, data = on ? mask : 0x00000000;
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nvkm_mask(device, 0x40988c, mask, data);
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nvkm_rd32(device, 0x40988c);
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nvkm_mask(device, 0x41a88c, mask, data);
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nvkm_rd32(device, 0x41a88c);
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nvkm_mask(device, 0x408a14, mask, data);
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nvkm_rd32(device, 0x408a14);
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}
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const struct gf100_grctx_func
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gv100_grctx = {
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.unkn88c = gv100_grctx_unkn88c,
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.main = gf100_grctx_generate_main,
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.unkn = gv100_grctx_generate_unkn,
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.sw_veid_bundle_init = gv100_grctx_pack_sw_veid_bundle_init,
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.bundle = gm107_grctx_generate_bundle,
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.bundle_size = 0x3000,
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.bundle_min_gpm_fifo_depth = 0x180,
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.bundle_token_limit = 0x1680,
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.pagepool = gp100_grctx_generate_pagepool,
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.pagepool_size = 0x20000,
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.attrib = gv100_grctx_generate_attrib,
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.attrib_nr_max = 0x6c0,
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.attrib_nr = 0x480,
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.alpha_nr_max = 0xc00,
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.alpha_nr = 0x800,
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.gfxp_nr = 0xd10,
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.sm_id = gv100_grctx_generate_sm_id,
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.rop_mapping = gv100_grctx_generate_rop_mapping,
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.dist_skip_table = gm200_grctx_generate_dist_skip_table,
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.r406500 = gm200_grctx_generate_r406500,
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.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
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.smid_config = gp100_grctx_generate_smid_config,
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.r400088 = gv100_grctx_generate_r400088,
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};
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@ -987,7 +987,7 @@ gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
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}
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static const struct nvkm_enum gf100_mp_warp_error[] = {
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const struct nvkm_enum gf100_mp_warp_error[] = {
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{ 0x01, "STACK_ERROR" },
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{ 0x02, "API_STACK_ERROR" },
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{ 0x03, "RET_EMPTY_STACK_ERROR" },
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@ -1012,7 +1012,7 @@ static const struct nvkm_enum gf100_mp_warp_error[] = {
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{}
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};
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static const struct nvkm_bitfield gf100_mp_global_error[] = {
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const struct nvkm_bitfield gf100_mp_global_error[] = {
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{ 0x00000001, "SM_TO_SM_FAULT" },
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{ 0x00000002, "L1_ERROR" },
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{ 0x00000004, "MULTIPLE_WARP_ERRORS" },
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@ -2113,6 +2113,9 @@ gf100_gr_init(struct gf100_gr *gr)
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int gpc, tpc, rop;
|
||||
|
||||
if (gr->func->init_419bd8)
|
||||
gr->func->init_419bd8(gr);
|
||||
|
||||
gr->func->init_gpc_mmu(gr);
|
||||
|
||||
if (gr->fuc_sw_nonctx)
|
||||
|
|
@ -2213,6 +2216,9 @@ gf100_gr_init(struct gf100_gr *gr)
|
|||
|
||||
gf100_gr_zbc_init(gr);
|
||||
|
||||
if (gr->func->init_4188a4)
|
||||
gr->func->init_4188a4(gr);
|
||||
|
||||
return gf100_gr_init_ctxctl(gr);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -149,6 +149,7 @@ struct gf100_gr_func {
|
|||
void (*oneinit_tiles)(struct gf100_gr *);
|
||||
void (*oneinit_sm_id)(struct gf100_gr *);
|
||||
int (*init)(struct gf100_gr *);
|
||||
void (*init_419bd8)(struct gf100_gr *);
|
||||
void (*init_gpc_mmu)(struct gf100_gr *);
|
||||
void (*init_r405a14)(struct gf100_gr *);
|
||||
void (*init_bios)(struct gf100_gr *);
|
||||
|
|
@ -170,6 +171,7 @@ struct gf100_gr_func {
|
|||
void (*init_504430)(struct gf100_gr *, int gpc, int tpc);
|
||||
void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc);
|
||||
void (*init_400054)(struct gf100_gr *);
|
||||
void (*init_4188a4)(struct gf100_gr *);
|
||||
void (*trap_mp)(struct gf100_gr *, int gpc, int tpc);
|
||||
void (*set_hww_esr_report_mask)(struct gf100_gr *);
|
||||
const struct gf100_gr_pack *mmio;
|
||||
|
|
@ -266,7 +268,7 @@ extern const struct nvkm_object_func gf100_fermi;
|
|||
struct gf100_gr_init {
|
||||
u32 addr;
|
||||
u8 count;
|
||||
u8 pitch;
|
||||
u32 pitch;
|
||||
u32 data;
|
||||
};
|
||||
|
||||
|
|
@ -337,6 +339,8 @@ extern const struct gf100_gr_init gf100_gr_init_fe_1[];
|
|||
extern const struct gf100_gr_init gf100_gr_init_pe_1[];
|
||||
void gf100_gr_init_gpc_mmu(struct gf100_gr *);
|
||||
void gf100_gr_trap_mp(struct gf100_gr *, int, int);
|
||||
extern const struct nvkm_bitfield gf100_mp_global_error[];
|
||||
extern const struct nvkm_enum gf100_mp_warp_error[];
|
||||
|
||||
extern const struct gf100_gr_init gf104_gr_init_ds_0[];
|
||||
extern const struct gf100_gr_init gf104_gr_init_tex_0[];
|
||||
|
|
|
|||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright 2018 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "gf100.h"
|
||||
#include "ctxgf100.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
static void
|
||||
gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
|
||||
{
|
||||
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730));
|
||||
u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734));
|
||||
const struct nvkm_enum *warp;
|
||||
char glob[128];
|
||||
|
||||
nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
|
||||
warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
|
||||
|
||||
nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
|
||||
"global %08x [%s] warp %04x [%s]\n",
|
||||
gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
|
||||
|
||||
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730), 0x00000000);
|
||||
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734), gerr);
|
||||
}
|
||||
|
||||
static void
|
||||
gv100_gr_init_4188a4(struct gf100_gr *gr)
|
||||
{
|
||||
struct nvkm_device *device = gr->base.engine.subdev.device;
|
||||
nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000);
|
||||
}
|
||||
|
||||
static void
|
||||
gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
|
||||
{
|
||||
struct nvkm_device *device = gr->base.engine.subdev.device;
|
||||
int sm;
|
||||
for (sm = 0; sm < 0x100; sm += 0x80) {
|
||||
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64);
|
||||
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001);
|
||||
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
|
||||
{
|
||||
struct nvkm_device *device = gr->base.engine.subdev.device;
|
||||
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000);
|
||||
}
|
||||
|
||||
static void
|
||||
gv100_gr_init_419bd8(struct gf100_gr *gr)
|
||||
{
|
||||
struct nvkm_device *device = gr->base.engine.subdev.device;
|
||||
nvkm_mask(device, 0x419bd8, 0x00000700, 0x00000000);
|
||||
}
|
||||
|
||||
static const struct gf100_gr_func
|
||||
gv100_gr = {
|
||||
.oneinit_tiles = gm200_gr_oneinit_tiles,
|
||||
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
|
||||
.init = gf100_gr_init,
|
||||
.init_419bd8 = gv100_gr_init_419bd8,
|
||||
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
|
||||
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
|
||||
.init_zcull = gf117_gr_init_zcull,
|
||||
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
|
||||
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
|
||||
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
|
||||
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
|
||||
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
|
||||
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
|
||||
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
|
||||
.init_504430 = gv100_gr_init_504430,
|
||||
.init_shader_exceptions = gv100_gr_init_shader_exceptions,
|
||||
.init_4188a4 = gv100_gr_init_4188a4,
|
||||
.trap_mp = gv100_gr_trap_mp,
|
||||
.rops = gm200_gr_rops,
|
||||
.gpc_nr = 6,
|
||||
.tpc_nr = 5,
|
||||
.ppc_nr = 3,
|
||||
.grctx = &gv100_grctx,
|
||||
.zbc = &gp102_gr_zbc,
|
||||
.sclass = {
|
||||
{ -1, -1, FERMI_TWOD_A },
|
||||
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
|
||||
{ -1, -1, VOLTA_A, &gf100_fermi },
|
||||
{ -1, -1, VOLTA_COMPUTE_A },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
int
|
||||
gv100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
|
||||
{
|
||||
return gm200_gr_new_(&gv100_gr, device, index, pgr);
|
||||
}
|
||||
|
|
@ -506,6 +506,7 @@ nvkm_msgqueue_new(u32 version, struct nvkm_falcon *falcon,
|
|||
break;
|
||||
case 0x0148cdec:
|
||||
case 0x015ccf3e:
|
||||
case 0x0167d263:
|
||||
ret = msgqueue_0148cdec_new(falcon, sb, queue);
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -65,3 +65,24 @@ MODULE_FIRMWARE("nvidia/gp108/nvdec/scrubber.bin");
|
|||
MODULE_FIRMWARE("nvidia/gp108/sec2/desc.bin");
|
||||
MODULE_FIRMWARE("nvidia/gp108/sec2/image.bin");
|
||||
MODULE_FIRMWARE("nvidia/gp108/sec2/sig.bin");
|
||||
|
||||
MODULE_FIRMWARE("nvidia/gv100/acr/bl.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/acr/unload_bl.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/acr/ucode_load.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/acr/ucode_unload.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/sec2/desc.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/sec2/image.bin");
|
||||
MODULE_FIRMWARE("nvidia/gv100/sec2/sig.bin");
|
||||
|
|
|
|||
Loading…
Reference in New Issue