LoongArch: KVM: Add PCHPIC read and write functions
Upstream: no Implementation of IPI interrupt controller address space read and write function simulation. Implement interrupt injection interface under loongarch. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
This commit is contained in:
Xianglai Li
parent
c4f21bdb97
commit
d50ffb8488
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@ -35,6 +35,22 @@
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#define KVM_HALT_POLL_NS_DEFAULT 500000
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#define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(1)
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_LOONGARCH_IRQ_TYPE_SHIFT 24
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#define KVM_LOONGARCH_IRQ_TYPE_MASK 0xff
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#define KVM_LOONGARCH_IRQ_VCPU_SHIFT 16
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#define KVM_LOONGARCH_IRQ_VCPU_MASK 0xff
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#define KVM_LOONGARCH_IRQ_NUM_SHIFT 0
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#define KVM_LOONGARCH_IRQ_NUM_MASK 0xffff
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/* irq_type field */
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#define KVM_LOONGARCH_IRQ_TYPE_CPU_IP 0
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#define KVM_LOONGARCH_IRQ_TYPE_CPU_IO 1
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#define KVM_LOONGARCH_IRQ_TYPE_HT 2
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#define KVM_LOONGARCH_IRQ_TYPE_MSI 3
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#define KVM_LOONGARCH_IRQ_TYPE_IOAPIC 4
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#define KVM_LOONGARCH_IRQ_TYPE_ROUTE 5
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#define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
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KVM_GUESTDBG_USE_SW_BP | KVM_GUESTDBG_SINGLESTEP)
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struct kvm_vm_stat {
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@ -45,6 +61,8 @@ struct kvm_vm_stat {
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u64 ipi_write_exits;
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u64 extioi_read_exits;
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u64 extioi_write_exits;
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u64 pch_pic_read_exits;
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u64 pch_pic_write_exits;
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};
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struct kvm_vcpu_stat {
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@ -8,6 +8,35 @@
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#include <kvm/iodev.h>
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#define PCH_PIC_SIZE 0x3e8
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#define PCH_PIC_INT_ID_START 0x0
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#define PCH_PIC_INT_ID_END 0x7
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#define PCH_PIC_MASK_START 0x20
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#define PCH_PIC_MASK_END 0x27
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#define PCH_PIC_HTMSI_EN_START 0x40
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#define PCH_PIC_HTMSI_EN_END 0x47
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#define PCH_PIC_EDGE_START 0x60
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#define PCH_PIC_EDGE_END 0x67
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#define PCH_PIC_CLEAR_START 0x80
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#define PCH_PIC_CLEAR_END 0x87
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#define PCH_PIC_AUTO_CTRL0_START 0xc0
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#define PCH_PIC_AUTO_CTRL0_END 0xc7
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#define PCH_PIC_AUTO_CTRL1_START 0xe0
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#define PCH_PIC_AUTO_CTRL1_END 0xe7
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#define PCH_PIC_ROUTE_ENTRY_START 0x100
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#define PCH_PIC_ROUTE_ENTRY_END 0x13f
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#define PCH_PIC_HTMSI_VEC_START 0x200
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#define PCH_PIC_HTMSI_VEC_END 0x23f
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#define PCH_PIC_INT_IRR_START 0x380
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#define PCH_PIC_INT_IRR_END 0x38f
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#define PCH_PIC_INT_ISR_START 0x3a0
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#define PCH_PIC_INT_ISR_END 0x3af
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#define PCH_PIC_POLARITY_START 0x3e0
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#define PCH_PIC_POLARITY_END 0x3e7
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#define PCH_PIC_INT_ID_VAL 0x7000000UL
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#define PCH_PIC_INT_ID_VER 0x1UL
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struct loongarch_pch_pic {
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spinlock_t lock;
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struct kvm *kvm;
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@ -26,5 +55,7 @@ struct loongarch_pch_pic {
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uint64_t pch_pic_base;
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};
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void pch_pic_set_irq(struct loongarch_pch_pic *s, int irq, int level);
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void pch_msi_set_irq(struct kvm *kvm, int irq, int level);
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int kvm_loongarch_register_pch_pic_device(void);
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#endif /* LOONGARCH_PCH_PIC_H */
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@ -19,6 +19,7 @@
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_DIRTY_LOG_PAGE_OFFSET 64
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#define __KVM_HAVE_IRQ_LINE
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#define KVM_GUESTDBG_USE_SW_BP 0x00010000
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/*
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@ -223,9 +223,9 @@ static int kvm_loongarch_ipi_read(struct kvm_vcpu *vcpu,
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return ret;
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}
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static void send_ipi_data(struct kvm_vcpu *vcpu, gpa_t addr, uint64_t data)
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static int send_ipi_data(struct kvm_vcpu *vcpu, gpa_t addr, uint64_t data)
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{
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int i;
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int i, ret;
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uint32_t val = 0, mask = 0;
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/*
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* Bit 27-30 is mask for byte writing.
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@ -233,8 +233,11 @@ static void send_ipi_data(struct kvm_vcpu *vcpu, gpa_t addr, uint64_t data)
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*/
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if ((data >> 27) & 0xf) {
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/* Read the old val */
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kvm_io_bus_read(vcpu, KVM_IOCSR_BUS, addr, sizeof(val), &val);
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ret = kvm_io_bus_read(vcpu, KVM_IOCSR_BUS, addr, sizeof(val), &val);
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if (unlikely(ret)) {
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kvm_err("%s: : read date from addr %llx failed\n", __func__, addr);
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return ret;
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}
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/* Construct the mask by scanning the bit 27-30 */
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for (i = 0; i < 4; i++) {
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if (data & (0x1 << (27 + i)))
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@ -245,41 +248,48 @@ static void send_ipi_data(struct kvm_vcpu *vcpu, gpa_t addr, uint64_t data)
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}
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val |= ((uint32_t)(data >> 32) & ~mask);
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kvm_io_bus_write(vcpu, KVM_IOCSR_BUS, addr, sizeof(val), &val);
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ret = kvm_io_bus_write(vcpu, KVM_IOCSR_BUS, addr, sizeof(val), &val);
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if (unlikely(ret))
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kvm_err("%s: : write date to addr %llx failed\n", __func__, addr);
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return ret;
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}
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static void mail_send(struct kvm *kvm, uint64_t data)
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static int mail_send(struct kvm *kvm, uint64_t data)
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{
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struct kvm_vcpu *vcpu;
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int cpu, mailbox;
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int offset;
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int offset, ret;
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cpu = ((data & 0xffffffff) >> 16) & 0x3ff;
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vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu);
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if (unlikely(vcpu == NULL)) {
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kvm_err("%s: invalid target cpu: %d\n", __func__, cpu);
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return;
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return -EINVAL;
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}
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mailbox = ((data & 0xffffffff) >> 2) & 0x7;
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offset = SMP_MAILBOX + CORE_BUF_20 + mailbox * 4;
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send_ipi_data(vcpu, offset, data);
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ret = send_ipi_data(vcpu, offset, data);
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return ret;
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}
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static void any_send(struct kvm *kvm, uint64_t data)
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static int any_send(struct kvm *kvm, uint64_t data)
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{
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struct kvm_vcpu *vcpu;
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int cpu, offset;
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int cpu, offset, ret;
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cpu = ((data & 0xffffffff) >> 16) & 0x3ff;
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vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu);
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if (unlikely(vcpu == NULL)) {
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kvm_err("%s: invalid target cpu: %d\n", __func__, cpu);
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return;
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return -EINVAL;
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}
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offset = data & 0xffff;
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send_ipi_data(vcpu, offset, data);
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ret = send_ipi_data(vcpu, offset, data);
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return ret;
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}
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static int kvm_loongarch_mail_write(struct kvm_vcpu *vcpu,
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@ -287,6 +297,7 @@ static int kvm_loongarch_mail_write(struct kvm_vcpu *vcpu,
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gpa_t addr, int len, const void *val)
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{
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struct loongarch_ipi *ipi;
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int ret;
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ipi = vcpu->kvm->arch.ipi;
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if (!ipi) {
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@ -299,16 +310,18 @@ static int kvm_loongarch_mail_write(struct kvm_vcpu *vcpu,
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switch (addr) {
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case MAIL_SEND_OFFSET:
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mail_send(vcpu->kvm, *(uint64_t *)val);
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ret = mail_send(vcpu->kvm, *(uint64_t *)val);
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break;
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case ANY_SEND_OFFSET:
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any_send(vcpu->kvm, *(uint64_t *)val);
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ret = any_send(vcpu->kvm, *(uint64_t *)val);
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break;
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default:
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kvm_err("%s: invalid addr %llx!\n", __func__, addr);
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ret = -EINVAL;
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break;
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}
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return 0;
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return ret;
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}
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static const struct kvm_io_device_ops kvm_loongarch_ipi_ops = {
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@ -8,18 +8,306 @@
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#include <asm/kvm_vcpu.h>
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#include <linux/count_zeros.h>
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/* update the isr according to irq level and route irq to extioi */
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static void pch_pic_update_irq(struct loongarch_pch_pic *s, int irq, int level)
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{
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u64 mask = (1 << irq);
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/*
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* set isr and route irq to extioi and
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* the route table is in htmsi_vector[]
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*/
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if (level) {
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if (mask & s->irr & ~s->mask) {
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s->isr |= mask;
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irq = s->htmsi_vector[irq];
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extioi_set_irq(s->kvm->arch.extioi, irq, level);
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}
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} else {
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if (mask & s->isr & ~s->irr) {
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s->isr &= ~mask;
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irq = s->htmsi_vector[irq];
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extioi_set_irq(s->kvm->arch.extioi, irq, level);
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}
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}
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}
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/* msi irq handler */
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void pch_msi_set_irq(struct kvm *kvm, int irq, int level)
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{
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extioi_set_irq(kvm->arch.extioi, irq, level);
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}
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/* called when a irq is triggered in pch pic */
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void pch_pic_set_irq(struct loongarch_pch_pic *s, int irq, int level)
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{
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u64 mask = (1 << irq);
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spin_lock(&s->lock);
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if (level)
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/* set irr */
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s->irr |= mask;
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else {
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/* 0 level signal in edge triggered irq does not mean to clear irq
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* The irr register variable is cleared when the cpu writes to the
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* PCH_PIC_CLEAR_START address area
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*/
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if (s->edge & mask) {
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spin_unlock(&s->lock);
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return;
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}
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s->irr &= ~mask;
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}
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pch_pic_update_irq(s, irq, level);
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spin_unlock(&s->lock);
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}
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/* update batch irqs, the irq_mask is a bitmap of irqs */
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static void pch_pic_update_batch_irqs(struct loongarch_pch_pic *s, u64 irq_mask, int level)
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{
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int irq, bits;
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/* find each irq by irqs bitmap and update each irq */
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bits = sizeof(irq_mask) * 8;
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irq = find_first_bit((void *)&irq_mask, bits);
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while (irq < bits) {
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pch_pic_update_irq(s, irq, level);
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bitmap_clear((void *)&irq_mask, irq, 1);
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irq = find_first_bit((void *)&irq_mask, bits);
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}
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}
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/*
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* pch pic register is 64-bit, but it is accessed by 32-bit,
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* so we use high to get whether low or high 32 bits we want
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* to read.
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*/
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static u32 pch_pic_read_reg(u64 *s, int high)
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{
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u64 val = *s;
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/* read the high 32 bits when the high is 1 */
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return high ? (u32)(val >> 32) : (u32)val;
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}
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/*
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* pch pic register is 64-bit, but it is accessed by 32-bit,
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* so we use high to get whether low or high 32 bits we want
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* to write.
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*/
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static u32 pch_pic_write_reg(u64 *s, int high, u32 v)
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{
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u64 val = *s, data = v;
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if (high) {
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/*
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* Clear val high 32 bits
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* write the high 32 bits when the high is 1
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*/
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*s = (val << 32 >> 32) | (data << 32);
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val >>= 32;
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} else
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/*
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* Clear val low 32 bits
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* write the low 32 bits when the high is 0
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*/
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*s = (val >> 32 << 32) | v;
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return (u32)val;
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}
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static int loongarch_pch_pic_write(struct loongarch_pch_pic *s, gpa_t addr,
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int len, const void *val)
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{
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u32 old, data, offset, index;
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u64 irq;
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int ret;
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ret = 0;
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data = *(u32 *)val;
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offset = addr - s->pch_pic_base;
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spin_lock(&s->lock);
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switch (offset) {
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case PCH_PIC_MASK_START ... PCH_PIC_MASK_END:
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offset -= PCH_PIC_MASK_START;
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/* get whether high or low 32 bits we want to write */
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index = offset >> 2;
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old = pch_pic_write_reg(&s->mask, index, data);
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/* enable irq when mask value change to 0 */
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irq = (old & ~data) << (32 * index);
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pch_pic_update_batch_irqs(s, irq, 1);
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/* disable irq when mask value change to 1 */
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irq = (~old & data) << (32 * index);
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pch_pic_update_batch_irqs(s, irq, 0);
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break;
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case PCH_PIC_HTMSI_EN_START ... PCH_PIC_HTMSI_EN_END:
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offset -= PCH_PIC_HTMSI_EN_START;
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index = offset >> 2;
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pch_pic_write_reg(&s->htmsi_en, index, data);
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break;
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case PCH_PIC_EDGE_START ... PCH_PIC_EDGE_END:
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offset -= PCH_PIC_EDGE_START;
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index = offset >> 2;
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/* 1: edge triggered, 0: level triggered */
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pch_pic_write_reg(&s->edge, index, data);
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break;
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case PCH_PIC_CLEAR_START ... PCH_PIC_CLEAR_END:
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offset -= PCH_PIC_CLEAR_START;
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index = offset >> 2;
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/* write 1 to clear edge irq */
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old = pch_pic_read_reg(&s->irr, index);
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/*
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* get the irq bitmap which is edge triggered and
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* already set and to be cleared
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*/
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irq = old & pch_pic_read_reg(&s->edge, index) & data;
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/* write irr to the new state where irqs have been cleared */
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pch_pic_write_reg(&s->irr, index, old & ~irq);
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/* update cleared irqs */
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pch_pic_update_batch_irqs(s, irq, 0);
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break;
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case PCH_PIC_AUTO_CTRL0_START ... PCH_PIC_AUTO_CTRL0_END:
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offset -= PCH_PIC_AUTO_CTRL0_START;
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index = offset >> 2;
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/* we only use default mode: fixed interrupt distribution mode */
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pch_pic_write_reg(&s->auto_ctrl0, index, 0);
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break;
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case PCH_PIC_AUTO_CTRL1_START ... PCH_PIC_AUTO_CTRL1_END:
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offset -= PCH_PIC_AUTO_CTRL1_START;
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index = offset >> 2;
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/* we only use default mode: fixed interrupt distribution mode */
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pch_pic_write_reg(&s->auto_ctrl1, index, 0);
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break;
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case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END:
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offset -= PCH_PIC_ROUTE_ENTRY_START;
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/* only route to int0: extioi */
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s->route_entry[offset] = 1;
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break;
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case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END:
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/* route table to extioi */
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offset -= PCH_PIC_HTMSI_VEC_START;
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s->htmsi_vector[offset] = (u8)data;
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break;
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case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END:
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offset -= PCH_PIC_POLARITY_START;
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index = offset >> 2;
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/* we only use defalut value 0: high level triggered */
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pch_pic_write_reg(&s->polarity, index, 0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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spin_unlock(&s->lock);
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return ret;
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}
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static int kvm_loongarch_pch_pic_write(struct kvm_vcpu *vcpu,
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struct kvm_io_device *dev,
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gpa_t addr, int len, const void *val)
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{
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return 0;
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int ret;
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struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;
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if (!s) {
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kvm_err("%s: pch pic irqchip not valid!\n", __func__);
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return -EINVAL;
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}
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/* statistics of pch pic writing */
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||||
vcpu->kvm->stat.pch_pic_write_exits++;
|
||||
ret = loongarch_pch_pic_write(s, addr, len, val);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int loongarch_pch_pic_read(struct loongarch_pch_pic *s, gpa_t addr, int len, void *val)
|
||||
{
|
||||
int offset, index, ret = 0;
|
||||
u32 data = 0;
|
||||
u64 int_id = 0;
|
||||
|
||||
offset = addr - s->pch_pic_base;
|
||||
|
||||
spin_lock(&s->lock);
|
||||
switch (offset) {
|
||||
case PCH_PIC_INT_ID_START ... PCH_PIC_INT_ID_END:
|
||||
/* int id version */
|
||||
int_id |= (u64)PCH_PIC_INT_ID_VER << 32;
|
||||
/* irq number */
|
||||
int_id |= (u64)31 << (32 + 16);
|
||||
/* int id value */
|
||||
int_id |= PCH_PIC_INT_ID_VAL;
|
||||
*(u64 *)val = int_id;
|
||||
break;
|
||||
case PCH_PIC_MASK_START ... PCH_PIC_MASK_END:
|
||||
offset -= PCH_PIC_MASK_START;
|
||||
index = offset >> 2;
|
||||
/* read mask reg */
|
||||
data = pch_pic_read_reg(&s->mask, index);
|
||||
*(u32 *)val = data;
|
||||
break;
|
||||
case PCH_PIC_HTMSI_EN_START ... PCH_PIC_HTMSI_EN_END:
|
||||
offset -= PCH_PIC_HTMSI_EN_START;
|
||||
index = offset >> 2;
|
||||
/* read htmsi enable reg */
|
||||
data = pch_pic_read_reg(&s->htmsi_en, index);
|
||||
*(u32 *)val = data;
|
||||
break;
|
||||
case PCH_PIC_EDGE_START ... PCH_PIC_EDGE_END:
|
||||
offset -= PCH_PIC_EDGE_START;
|
||||
index = offset >> 2;
|
||||
/* read edge enable reg */
|
||||
data = pch_pic_read_reg(&s->edge, index);
|
||||
*(u32 *)val = data;
|
||||
break;
|
||||
case PCH_PIC_AUTO_CTRL0_START ... PCH_PIC_AUTO_CTRL0_END:
|
||||
case PCH_PIC_AUTO_CTRL1_START ... PCH_PIC_AUTO_CTRL1_END:
|
||||
/* we only use default mode: fixed interrupt distribution mode */
|
||||
*(u32 *)val = 0;
|
||||
break;
|
||||
case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END:
|
||||
/* only route to int0: extioi */
|
||||
*(u8 *)val = 1;
|
||||
break;
|
||||
case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END:
|
||||
offset -= PCH_PIC_HTMSI_VEC_START;
|
||||
/* read htmsi vector */
|
||||
data = s->htmsi_vector[offset];
|
||||
*(u8 *)val = data;
|
||||
break;
|
||||
case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END:
|
||||
/* we only use defalut value 0: high level triggered */
|
||||
*(u32 *)val = 0;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
spin_unlock(&s->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int kvm_loongarch_pch_pic_read(struct kvm_vcpu *vcpu,
|
||||
struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, void *val)
|
||||
{
|
||||
return 0;
|
||||
int ret;
|
||||
struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;
|
||||
|
||||
if (!s) {
|
||||
kvm_err("%s: pch pic irqchip not valid!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* statistics of pch pic reading */
|
||||
vcpu->kvm->stat.pch_pic_read_exits++;
|
||||
ret = loongarch_pch_pic_read(s, addr, len, val);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct kvm_io_device_ops kvm_loongarch_pch_pic_ops = {
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
|
||||
#include <linux/kvm_host.h>
|
||||
#include <asm/kvm_mmu.h>
|
||||
#include <asm/kvm_extioi.h>
|
||||
#include <asm/kvm_pch_pic.h>
|
||||
|
||||
const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
|
||||
KVM_GENERIC_VM_STATS(),
|
||||
|
|
@ -104,3 +106,35 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
|
|||
{
|
||||
return -ENOIOCTLCMD;
|
||||
}
|
||||
|
||||
int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *data,
|
||||
bool line_status)
|
||||
{
|
||||
bool level;
|
||||
struct loongarch_pch_pic *s;
|
||||
int type, vcpu, irq, vcpus, val, ret = 0;
|
||||
|
||||
level = data->level;
|
||||
val = data->irq;
|
||||
s = kvm->arch.pch_pic;
|
||||
vcpus = atomic_read(&kvm->online_vcpus);
|
||||
|
||||
type = (val >> KVM_LOONGARCH_IRQ_TYPE_SHIFT) & KVM_LOONGARCH_IRQ_TYPE_MASK;
|
||||
vcpu = (val >> KVM_LOONGARCH_IRQ_VCPU_SHIFT) & KVM_LOONGARCH_IRQ_VCPU_MASK;
|
||||
irq = (val >> KVM_LOONGARCH_IRQ_NUM_SHIFT) & KVM_LOONGARCH_IRQ_NUM_MASK;
|
||||
|
||||
switch (type) {
|
||||
case KVM_LOONGARCH_IRQ_TYPE_IOAPIC:
|
||||
if (irq < KVM_IRQCHIP_NUM_PINS)
|
||||
pch_pic_set_irq(s, irq, level);
|
||||
else if (irq < 256)
|
||||
pch_msi_set_irq(kvm, irq, level);
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue