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ptp_qoriq: fix register memory map 

The 1588 timer on eTSEC Ethernet controller uses different
register memory map with DPAA Ethernet controller.
Now the new ENETC Ethernet controller uses same reigster
memory map with DPAA. To support ENETC, let's use register
memory map of DPAA/ENETC in default.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yangbo Lu 2019-02-12 12:24:01 +08:00 committed by David S. Miller
parent 2843bf5185
commit d4e176870b
2 changed files with 14 additions and 13 deletions
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11
drivers/ptp/ptp_qoriq.c
View File

@ -504,11 +504,12 @@ int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base,
ptp_qoriq->write = qoriq_write_be; ptp_qoriq->write = qoriq_write_be;
} }
if (of_device_is_compatible(node, "fsl,fman-ptp-timer")) { /* The eTSEC uses differnt memory map with DPAA/ENETC */
ptp_qoriq->regs.ctrl_regs = base + FMAN_CTRL_REGS_OFFSET; if (of_device_is_compatible(node, "fsl,etsec-ptp")) {
ptp_qoriq->regs.alarm_regs = base + FMAN_ALARM_REGS_OFFSET; ptp_qoriq->regs.ctrl_regs = base + ETSEC_CTRL_REGS_OFFSET;
ptp_qoriq->regs.fiper_regs = base + FMAN_FIPER_REGS_OFFSET; ptp_qoriq->regs.alarm_regs = base + ETSEC_ALARM_REGS_OFFSET;
ptp_qoriq->regs.etts_regs = base + FMAN_ETTS_REGS_OFFSET; ptp_qoriq->regs.fiper_regs = base + ETSEC_FIPER_REGS_OFFSET;
ptp_qoriq->regs.etts_regs = base + ETSEC_ETTS_REGS_OFFSET;
} else { } else {
ptp_qoriq->regs.ctrl_regs = base + CTRL_REGS_OFFSET; ptp_qoriq->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
ptp_qoriq->regs.alarm_regs = base + ALARM_REGS_OFFSET; ptp_qoriq->regs.alarm_regs = base + ALARM_REGS_OFFSET;

16
include/linux/fsl/ptp_qoriq.h
View File

@ -58,15 +58,15 @@ struct ptp_qoriq_registers {
}; };
/* Offset definitions for the four register groups */ /* Offset definitions for the four register groups */
#define CTRL_REGS_OFFSET 0x0 #define ETSEC_CTRL_REGS_OFFSET 0x0
#define ALARM_REGS_OFFSET 0x40 #define ETSEC_ALARM_REGS_OFFSET 0x40
#define FIPER_REGS_OFFSET 0x80 #define ETSEC_FIPER_REGS_OFFSET 0x80
#define ETTS_REGS_OFFSET 0xa0 #define ETSEC_ETTS_REGS_OFFSET 0xa0
#define FMAN_CTRL_REGS_OFFSET 0x80 #define CTRL_REGS_OFFSET 0x80
#define FMAN_ALARM_REGS_OFFSET 0xb8 #define ALARM_REGS_OFFSET 0xb8
#define FMAN_FIPER_REGS_OFFSET 0xd0 #define FIPER_REGS_OFFSET 0xd0
#define FMAN_ETTS_REGS_OFFSET 0xe0 #define ETTS_REGS_OFFSET 0xe0
/* Bit definitions for the TMR_CTRL register */ /* Bit definitions for the TMR_CTRL register */