mlxsw: spectrum: Add Spectrum-2 ASIC port type-speed operations
Add Spectrum-2 ASIC port type-speed operations.
Since multiple ethtool link modes are represented using a single bit in the
ASIC, the driver forces the user to configure all types per a specific
speed. For example, if the user wants to advertise 100Gbps 4-lanes speed,
he should advertise all the types of 100Gbps 4-lanes speed that are
supported by the ASIC as shown below:
Supported ethtool bits for 100Gbps 4-lanes:
0x1000000000 100000baseKR4 Full
0x2000000000 100000baseSR4 Full
0x4000000000 100000baseCR4 Full
0x8000000000 100000baseLR4_ER4 Full
Command for advertising 100Gbps 4-lanes:
ethtool -s enp3s0np1 advertise 0xF000000000
Signed-off-by: Shalom Toledo <shalomt@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shalom Toledo
David S. Miller
parent
9ce8439718
commit
d3eaf1085a
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@ -2607,6 +2607,334 @@ mlxsw_sp1_port_type_speed_ops = {
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.reg_ptys_eth_unpack = mlxsw_sp1_reg_ptys_eth_unpack,
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};
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
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ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
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ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {
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ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_5gbase_r[] = {
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ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
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ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
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ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
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ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
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ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
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ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
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ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
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ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
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ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
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ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
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ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
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ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
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ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
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static const enum ethtool_link_mode_bit_indices
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mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
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ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
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ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
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ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
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ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
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};
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#define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
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ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
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struct mlxsw_sp2_port_link_mode {
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const enum ethtool_link_mode_bit_indices *mask_ethtool;
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int m_ethtool_len;
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u32 mask;
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u32 speed;
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};
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static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_sgmii_100m,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
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.speed = SPEED_100,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
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.speed = SPEED_1000,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
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.speed = SPEED_2500,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_5gbase_r,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
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.speed = SPEED_5000,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
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.speed = SPEED_10000,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
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.speed = SPEED_40000,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
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.speed = SPEED_25000,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
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.speed = SPEED_50000,
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},
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{
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.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
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.mask_ethtool = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
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.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
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.speed = SPEED_100000,
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},
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};
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#define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
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static void
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mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
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u32 ptys_eth_proto,
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struct ethtool_link_ksettings *cmd)
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{
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ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
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ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
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}
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static void
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mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
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unsigned long *mode)
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{
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int i;
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for (i = 0; i < link_mode->m_ethtool_len; i++)
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__set_bit(link_mode->mask_ethtool[i], mode);
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}
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static void
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mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
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unsigned long *mode)
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{
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int i;
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for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
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if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
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mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
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mode);
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}
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}
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static void
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mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
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u32 ptys_eth_proto,
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struct ethtool_link_ksettings *cmd)
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{
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u32 speed = SPEED_UNKNOWN;
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u8 duplex = DUPLEX_UNKNOWN;
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int i;
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if (!carrier_ok)
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goto out;
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for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
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if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) {
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speed = mlxsw_sp2_port_link_mode[i].speed;
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duplex = DUPLEX_FULL;
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break;
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}
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}
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out:
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cmd->base.speed = speed;
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cmd->base.duplex = duplex;
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}
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static bool
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mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
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const unsigned long *mode)
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{
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int cnt = 0;
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int i;
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for (i = 0; i < link_mode->m_ethtool_len; i++) {
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if (test_bit(link_mode->mask_ethtool[i], mode))
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cnt++;
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}
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return cnt == link_mode->m_ethtool_len;
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}
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static u32
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mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp,
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const struct ethtool_link_ksettings *cmd)
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{
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u32 ptys_proto = 0;
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int i;
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for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
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if (mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
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cmd->link_modes.advertising))
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ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
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}
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return ptys_proto;
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}
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static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 speed)
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{
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u32 ptys_proto = 0;
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int i;
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for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
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if (speed == mlxsw_sp2_port_link_mode[i].speed)
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ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
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}
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return ptys_proto;
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}
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static u32
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mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
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{
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u32 ptys_proto = 0;
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int i;
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for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
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if (mlxsw_sp2_port_link_mode[i].speed <= upper_speed)
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ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
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}
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return ptys_proto;
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}
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static int
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mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
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u32 *base_speed)
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{
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char ptys_pl[MLXSW_REG_PTYS_LEN];
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u32 eth_proto_cap;
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int err;
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/* In Spectrum-2, the speed of 1x can change from port to port, so query
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* it from firmware.
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*/
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mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false);
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err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
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if (err)
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return err;
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mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL);
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if (eth_proto_cap &
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MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) {
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*base_speed = MLXSW_SP_PORT_BASE_SPEED_50G;
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return 0;
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}
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if (eth_proto_cap &
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MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) {
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*base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
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return 0;
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}
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return -EIO;
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}
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static void
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mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
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u8 local_port, u32 proto_admin,
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bool autoneg)
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{
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mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
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}
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static void
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mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
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u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
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u32 *p_eth_proto_oper)
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{
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mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
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p_eth_proto_admin, p_eth_proto_oper);
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}
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static const struct mlxsw_sp_port_type_speed_ops
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mlxsw_sp2_port_type_speed_ops = {
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.from_ptys_supported_port = mlxsw_sp2_from_ptys_supported_port,
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.from_ptys_link = mlxsw_sp2_from_ptys_link,
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.from_ptys_speed_duplex = mlxsw_sp2_from_ptys_speed_duplex,
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.to_ptys_advert_link = mlxsw_sp2_to_ptys_advert_link,
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.to_ptys_speed = mlxsw_sp2_to_ptys_speed,
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.to_ptys_upper_speed = mlxsw_sp2_to_ptys_upper_speed,
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.port_speed_base = mlxsw_sp2_port_speed_base,
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.reg_ptys_eth_pack = mlxsw_sp2_reg_ptys_eth_pack,
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.reg_ptys_eth_unpack = mlxsw_sp2_reg_ptys_eth_unpack,
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};
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static void
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mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
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struct ethtool_link_ksettings *cmd)
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@ -4189,7 +4517,7 @@ static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
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mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
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mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
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mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
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mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
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mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
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return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
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}
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@ -34,6 +34,7 @@
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#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
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#define MLXSW_SP_PORT_BASE_SPEED_25G 25000 /* Mb/s */
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#define MLXSW_SP_PORT_BASE_SPEED_50G 50000 /* Mb/s */
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#define MLXSW_SP_KVD_LINEAR_SIZE 98304 /* entries */
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||||
#define MLXSW_SP_KVD_GRANULARITY 128
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||||
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Reference in New Issue