clk: hip04: add clock driver
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
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obj-$(CONFIG_COMMON_CLK_AT91) += at91/
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obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
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obj-$(CONFIG_ARCH_HIP04) += hisilicon/
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obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_MMP) += mmp/
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@ -2,4 +2,7 @@
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# Hisilicon Clock specific Makefile
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#
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obj-y += clk.o clkgate-separated.o clk-hi3620.o
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obj-y += clk.o clkgate-separated.o
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obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
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obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
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@ -0,0 +1,54 @@
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/*
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* Hisilicon HiP04 clock driver
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*
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* Copyright (c) 2013-2014 Hisilicon Limited.
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* Copyright (c) 2013-2014 Linaro Limited.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <dt-bindings/clock/hip04-clock.h>
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#include "clk.h"
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/* fixed rate clocks */
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static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
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{ HIP04_OSC50M, "osc50m", NULL, CLK_IS_ROOT, 50000000, },
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{ HIP04_CLK_50M, "clk50m", NULL, CLK_IS_ROOT, 50000000, },
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{ HIP04_CLK_168M, "clk168m", NULL, CLK_IS_ROOT, 168750000, },
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};
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static void __init hip04_clk_init(struct device_node *np)
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{
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hisi_clk_init(np, HIP04_NR_CLKS);
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hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
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ARRAY_SIZE(hip04_fixed_rate_clks),
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NULL);
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}
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CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2013-2014 Hisilicon Limited.
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* Copyright (c) 2013-2014 Linaro Limited.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef __DTS_HIP04_CLOCK_H
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#define __DTS_HIP04_CLOCK_H
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#define HIP04_NONE_CLOCK 0
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/* fixed rate & fixed factor clocks */
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#define HIP04_OSC50M 1
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#define HIP04_CLK_50M 2
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#define HIP04_CLK_168M 3
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#define HIP04_NR_CLKS 64
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#endif /* __DTS_HIP04_CLOCK_H */
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