drm/radeon: rework GPU reset on r6xx/r7xx
Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
410a3418a8
commit
d3cb781e83
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@ -1266,122 +1266,22 @@ void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
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WREG32(R600_BIOS_3_SCRATCH, tmp);
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}
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/* We doesn't check that the GPU really needs a reset we simply do the
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* reset, it's up to the caller to determine if the GPU needs one. We
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* might add an helper function to check that.
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*/
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static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
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static void r600_print_gpu_status_regs(struct radeon_device *rdev)
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{
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u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
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S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
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S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
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S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
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S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
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S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
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S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
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S_008010_GUI_ACTIVE(1);
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u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
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S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
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S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
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S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
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S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
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S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
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S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
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S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
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u32 tmp;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return;
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dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
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RREG32(R_008010_GRBM_STATUS));
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RREG32(R_008010_GRBM_STATUS));
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dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
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RREG32(R_008014_GRBM_STATUS2));
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RREG32(R_008014_GRBM_STATUS2));
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
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RREG32(R_000E50_SRBM_STATUS));
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RREG32(R_000E50_SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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/* Disable CP parsing/prefetching */
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
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/* Check if any of the rendering block is busy and reset it */
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if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
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(RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
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tmp = S_008020_SOFT_RESET_CR(1) |
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S_008020_SOFT_RESET_DB(1) |
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S_008020_SOFT_RESET_CB(1) |
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S_008020_SOFT_RESET_PA(1) |
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S_008020_SOFT_RESET_SC(1) |
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S_008020_SOFT_RESET_SMX(1) |
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S_008020_SOFT_RESET_SPI(1) |
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S_008020_SOFT_RESET_SX(1) |
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S_008020_SOFT_RESET_SH(1) |
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S_008020_SOFT_RESET_TC(1) |
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S_008020_SOFT_RESET_TA(1) |
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S_008020_SOFT_RESET_VC(1) |
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S_008020_SOFT_RESET_VGT(1);
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dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(R_008020_GRBM_SOFT_RESET, tmp);
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RREG32(R_008020_GRBM_SOFT_RESET);
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mdelay(15);
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WREG32(R_008020_GRBM_SOFT_RESET, 0);
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}
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/* Reset CP (we always reset CP) */
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tmp = S_008020_SOFT_RESET_CP(1);
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dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(R_008020_GRBM_SOFT_RESET, tmp);
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RREG32(R_008020_GRBM_SOFT_RESET);
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mdelay(15);
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WREG32(R_008020_GRBM_SOFT_RESET, 0);
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dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
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RREG32(R_008010_GRBM_STATUS));
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dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
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RREG32(R_008014_GRBM_STATUS2));
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
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RREG32(R_000E50_SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
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RREG32(CP_STALLED_STAT2));
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dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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}
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static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
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{
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u32 tmp;
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if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
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return;
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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/* Disable DMA */
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tmp = RREG32(DMA_RB_CNTL);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL, tmp);
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/* Reset dma */
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if (rdev->family >= CHIP_RV770)
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WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
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else
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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RREG32(CP_STAT));
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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}
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@ -1389,9 +1289,12 @@ static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
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static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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{
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struct rv515_mc_save save;
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u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
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u32 tmp;
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int ret = 0;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
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reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP);
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if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
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reset_mask &= ~RADEON_RESET_DMA;
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@ -1401,6 +1304,8 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
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r600_print_gpu_status_regs(rdev);
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r600_set_bios_scratch_engine_hung(rdev, true);
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rv515_mc_stop(rdev, &save);
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@ -1408,20 +1313,127 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
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r600_gpu_soft_reset_gfx(rdev);
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/* Disable CP parsing/prefetching */
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if (rdev->family >= CHIP_RV770)
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
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else
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
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if (reset_mask & RADEON_RESET_DMA)
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r600_gpu_soft_reset_dma(rdev);
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/* disable the RLC */
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WREG32(RLC_CNTL, 0);
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if (reset_mask & RADEON_RESET_DMA) {
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/* Disable DMA */
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tmp = RREG32(DMA_RB_CNTL);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL, tmp);
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}
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mdelay(50);
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
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if (rdev->family >= CHIP_RV770)
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grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
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S_008020_SOFT_RESET_CB(1) |
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S_008020_SOFT_RESET_PA(1) |
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S_008020_SOFT_RESET_SC(1) |
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S_008020_SOFT_RESET_SPI(1) |
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S_008020_SOFT_RESET_SX(1) |
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S_008020_SOFT_RESET_SH(1) |
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S_008020_SOFT_RESET_TC(1) |
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S_008020_SOFT_RESET_TA(1) |
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S_008020_SOFT_RESET_VC(1) |
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S_008020_SOFT_RESET_VGT(1);
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else
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grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
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S_008020_SOFT_RESET_DB(1) |
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S_008020_SOFT_RESET_CB(1) |
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S_008020_SOFT_RESET_PA(1) |
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S_008020_SOFT_RESET_SC(1) |
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S_008020_SOFT_RESET_SMX(1) |
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S_008020_SOFT_RESET_SPI(1) |
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S_008020_SOFT_RESET_SX(1) |
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S_008020_SOFT_RESET_SH(1) |
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S_008020_SOFT_RESET_TC(1) |
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S_008020_SOFT_RESET_TA(1) |
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S_008020_SOFT_RESET_VC(1) |
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S_008020_SOFT_RESET_VGT(1);
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}
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if (reset_mask & RADEON_RESET_CP) {
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grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
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S_008020_SOFT_RESET_VGT(1);
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srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
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}
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if (reset_mask & RADEON_RESET_DMA) {
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if (rdev->family >= CHIP_RV770)
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srbm_soft_reset |= RV770_SOFT_RESET_DMA;
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else
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srbm_soft_reset |= SOFT_RESET_DMA;
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}
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if (grbm_soft_reset) {
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tmp = RREG32(R_008020_GRBM_SOFT_RESET);
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tmp |= grbm_soft_reset;
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dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(R_008020_GRBM_SOFT_RESET, tmp);
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tmp = RREG32(R_008020_GRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~grbm_soft_reset;
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WREG32(R_008020_GRBM_SOFT_RESET, tmp);
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tmp = RREG32(R_008020_GRBM_SOFT_RESET);
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}
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if (srbm_soft_reset) {
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tmp = RREG32(SRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(SRBM_SOFT_RESET, tmp);
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tmp = RREG32(SRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(SRBM_SOFT_RESET, tmp);
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tmp = RREG32(SRBM_SOFT_RESET);
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}
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/* Wait a little for things to settle down */
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mdelay(1);
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rv515_mc_resume(rdev, &save);
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udelay(50);
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r600_set_bios_scratch_engine_hung(rdev, false);
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#if 0
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
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if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
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ret = -EAGAIN;
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}
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return 0;
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if (reset_mask & RADEON_RESET_DMA) {
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if (!(RREG32(DMA_STATUS_REG) & DMA_IDLE))
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ret = -EAGAIN;
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}
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#endif
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if (!ret)
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r600_set_bios_scratch_engine_hung(rdev, false);
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r600_print_gpu_status_regs(rdev);
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return ret;
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}
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int r600_asic_reset(struct radeon_device *rdev)
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{
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return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
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RADEON_RESET_COMPUTE |
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RADEON_RESET_DMA |
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RADEON_RESET_CP));
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}
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bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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@ -1465,13 +1477,6 @@ bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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return radeon_ring_test_lockup(rdev, ring);
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}
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int r600_asic_reset(struct radeon_device *rdev)
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{
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return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
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RADEON_RESET_COMPUTE |
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RADEON_RESET_DMA));
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}
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u32 r6xx_remap_render_backend(struct radeon_device *rdev,
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u32 tiling_pipe_num,
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u32 max_rb_num,
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@ -182,6 +182,8 @@
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#define CP_COHER_BASE 0x85F8
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#define CP_DEBUG 0xC1FC
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#define R_0086D8_CP_ME_CNTL 0x86D8
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#define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26)
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#define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF)
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#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
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#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
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#define CP_ME_RAM_DATA 0xC160
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