arm64: dts: mediatek: Add I2C support for MT6797 SoC
Add I2C support for Mediatek MT6797 SoC. There are a total of 8 I2C controllers in this SoC (2 being shared) and they are same as the controllers present in MT6577 SoC. Hence, the driver support is added with DT fallback method. As per the datasheet, there are controllers with _imm prefix like i2c2_imm and i2c3_imm. These appears to be in different memory regions but sharing the same pins with i2c2 and i2c3 respectively. Since there is no clear evidence of what they really are, I've adapted the numbering/naming scheme from the downstream code by Mediatek. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200222162444.11590-3-manivannan.sadhasivam@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Manivannan Sadhasivam
Matthias Brugger
parent
b253761264
commit
d3c84299f2
|
|
@ -155,6 +155,62 @@
|
|||
<MT6797_GPIO233__FUNC_UTXD1>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins_a: i2c0 {
|
||||
pins0 {
|
||||
pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
|
||||
<MT6797_GPIO38__FUNC_SDA0_0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1 {
|
||||
pins1 {
|
||||
pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
|
||||
<MT6797_GPIO56__FUNC_SDA1_0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins_a: i2c2 {
|
||||
pins2 {
|
||||
pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
|
||||
<MT6797_GPIO95__FUNC_SDA2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3_pins_a: i2c3 {
|
||||
pins3 {
|
||||
pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
|
||||
<MT6797_GPIO74__FUNC_SCL3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins_a: i2c4 {
|
||||
pins4 {
|
||||
pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
|
||||
<MT6797_GPIO239__FUNC_SCL4_0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_pins_a: i2c5 {
|
||||
pins5 {
|
||||
pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
|
||||
<MT6797_GPIO241__FUNC_SCL5_0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c6_pins_a: i2c6 {
|
||||
pins6 {
|
||||
pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
|
||||
<MT6797_GPIO151__FUNC_SCL6_0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c7_pins_a: i2c7 {
|
||||
pins7 {
|
||||
pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
|
||||
<MT6797_GPIO153__FUNC_SCL7_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
scpsys: power-controller@10006000 {
|
||||
|
|
@ -233,6 +289,170 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11007000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <0>;
|
||||
reg = <0 0x11007000 0 0x1000>,
|
||||
<0 0x11000100 0 0x80>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C0>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11008000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <1>;
|
||||
reg = <0 0x11008000 0 0x1000>,
|
||||
<0 0x11000180 0 0x80>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C1>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@11009000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <8>;
|
||||
reg = <0 0x11009000 0 0x1000>,
|
||||
<0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C2>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C2_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c@1100d000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <9>;
|
||||
reg = <0 0x1100d000 0 0x1000>,
|
||||
<0 0x11000280 0 0x80>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C3>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C3_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@1100e000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <6>;
|
||||
reg = <0 0x1100e000 0 0x1000>,
|
||||
<0 0x11000500 0 0x80>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C_APPM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@11010000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <7>;
|
||||
reg = <0 0x11010000 0 0x1000>,
|
||||
<0 0x11000580 0 0x80>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@11011000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <4>;
|
||||
reg = <0 0x11011000 0 0x1000>,
|
||||
<0 0x11000300 0 0x80>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C4>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11013000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <2>;
|
||||
reg = <0 0x11013000 0 0x1000>,
|
||||
<0 0x11000400 0 0x80>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C2_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@11014000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <3>;
|
||||
reg = <0 0x11014000 0 0x1000>,
|
||||
<0 0x11000480 0 0x80>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C3_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@1101c000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <5>;
|
||||
reg = <0 0x1101c000 0 0x1000>,
|
||||
<0 0x11000380 0 0x80>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C5>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmsys: mmsys_config@14000000 {
|
||||
compatible = "mediatek,mt6797-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue