x86/sb_edac: Add row column translation for Broadwell
The sb_edac driver lacks translation for DIMM internal address. Add memory address translation for row/column/bank/bank_group on Broadwell. Signed-off-by: Youquan Song <youquan.song@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/all/20220722233338.341567-1-tony.luck@intel.com
This commit is contained in:
Youquan Song
Tony Luck
parent
d5f5e49953
commit
d389059685
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@ -335,6 +335,12 @@ struct sbridge_info {
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struct sbridge_channel {
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u32 ranks;
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u32 dimms;
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struct dimm {
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u32 rowbits;
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u32 colbits;
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u32 bank_xor_enable;
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u32 amap_fine;
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} dimm[MAX_DIMMS];
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};
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struct pci_id_descr {
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@ -1603,7 +1609,7 @@ static int __populate_dimms(struct mem_ctl_info *mci,
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banks = 8;
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for (i = 0; i < channels; i++) {
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u32 mtr;
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u32 mtr, amap = 0;
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int max_dimms_per_channel;
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@ -1615,6 +1621,7 @@ static int __populate_dimms(struct mem_ctl_info *mci,
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max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
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if (!pvt->pci_tad[i])
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continue;
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pci_read_config_dword(pvt->pci_tad[i], 0x8c, &amap);
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}
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for (j = 0; j < max_dimms_per_channel; j++) {
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@ -1627,6 +1634,7 @@ static int __populate_dimms(struct mem_ctl_info *mci,
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mtr_regs[j], &mtr);
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}
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edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
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if (IS_DIMM_PRESENT(mtr)) {
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if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
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sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n",
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@ -1661,6 +1669,11 @@ static int __populate_dimms(struct mem_ctl_info *mci,
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dimm->dtype = pvt->info.get_width(pvt, mtr);
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dimm->mtype = mtype;
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dimm->edac_mode = mode;
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pvt->channel[i].dimm[j].rowbits = order_base_2(rows);
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pvt->channel[i].dimm[j].colbits = order_base_2(cols);
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pvt->channel[i].dimm[j].bank_xor_enable =
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GET_BITFIELD(pvt->info.mcmtr, 9, 9);
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pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0);
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snprintf(dimm->label, sizeof(dimm->label),
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"CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
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pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
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@ -1922,6 +1935,99 @@ static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha)
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return NULL;
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}
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static u8 sb_close_row[] = {
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15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
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};
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static u8 sb_close_column[] = {
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3, 4, 5, 14, 19, 23, 24, 25, 26, 27
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};
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static u8 sb_open_row[] = {
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14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
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};
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static u8 sb_open_column[] = {
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3, 4, 5, 6, 7, 8, 9, 10, 11, 12
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};
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static u8 sb_open_fine_column[] = {
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3, 4, 5, 7, 8, 9, 10, 11, 12, 13
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};
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static int sb_bits(u64 addr, int nbits, u8 *bits)
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{
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int i, res = 0;
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for (i = 0; i < nbits; i++)
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res |= ((addr >> bits[i]) & 1) << i;
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return res;
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}
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static int sb_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
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{
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int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
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if (do_xor)
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ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
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return ret;
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}
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static bool sb_decode_ddr4(struct mem_ctl_info *mci, int ch, u8 rank,
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u64 rank_addr, char *msg)
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{
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int dimmno = 0;
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int row, col, bank_address, bank_group;
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struct sbridge_pvt *pvt;
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u32 bg0 = 0, rowbits = 0, colbits = 0;
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u32 amap_fine = 0, bank_xor_enable = 0;
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dimmno = (rank < 12) ? rank / 4 : 2;
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pvt = mci->pvt_info;
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amap_fine = pvt->channel[ch].dimm[dimmno].amap_fine;
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bg0 = amap_fine ? 6 : 13;
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rowbits = pvt->channel[ch].dimm[dimmno].rowbits;
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colbits = pvt->channel[ch].dimm[dimmno].colbits;
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bank_xor_enable = pvt->channel[ch].dimm[dimmno].bank_xor_enable;
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if (pvt->is_lockstep) {
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pr_warn_once("LockStep row/column decode is not supported yet!\n");
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msg[0] = '\0';
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return false;
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}
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if (pvt->is_close_pg) {
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row = sb_bits(rank_addr, rowbits, sb_close_row);
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col = sb_bits(rank_addr, colbits, sb_close_column);
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col |= 0x400; /* C10 is autoprecharge, always set */
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bank_address = sb_bank_bits(rank_addr, 8, 9, bank_xor_enable, 22, 28);
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bank_group = sb_bank_bits(rank_addr, 6, 7, bank_xor_enable, 20, 21);
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} else {
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row = sb_bits(rank_addr, rowbits, sb_open_row);
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if (amap_fine)
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col = sb_bits(rank_addr, colbits, sb_open_fine_column);
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else
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col = sb_bits(rank_addr, colbits, sb_open_column);
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bank_address = sb_bank_bits(rank_addr, 18, 19, bank_xor_enable, 22, 23);
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bank_group = sb_bank_bits(rank_addr, bg0, 17, bank_xor_enable, 20, 21);
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}
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row &= (1u << rowbits) - 1;
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sprintf(msg, "row:0x%x col:0x%x bank_addr:%d bank_group:%d",
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row, col, bank_address, bank_group);
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return true;
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}
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static bool sb_decode_ddr3(struct mem_ctl_info *mci, int ch, u8 rank,
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u64 rank_addr, char *msg)
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{
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pr_warn_once("DDR3 row/column decode not support yet!\n");
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msg[0] = '\0';
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return false;
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}
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static int get_memory_error_data(struct mem_ctl_info *mci,
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u64 addr,
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u8 *socket, u8 *ha,
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@ -1937,12 +2043,13 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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int interleave_mode, shiftup = 0;
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unsigned int sad_interleave[MAX_INTERLEAVE];
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u32 reg, dram_rule;
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u8 ch_way, sck_way, pkg, sad_ha = 0;
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u8 ch_way, sck_way, pkg, sad_ha = 0, rankid = 0;
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u32 tad_offset;
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u32 rir_way;
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u32 mb, gb;
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u64 ch_addr, offset, limit = 0, prv = 0;
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u64 rank_addr;
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enum mem_type mtype;
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/*
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* Step 0) Check if the address is at special memory ranges
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@ -2226,6 +2333,28 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);
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*rank = RIR_RNK_TGT(pvt->info.type, reg);
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if (pvt->info.type == BROADWELL) {
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if (pvt->is_close_pg)
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shiftup = 6;
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else
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shiftup = 13;
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rank_addr = ch_addr >> shiftup;
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rank_addr /= (1 << rir_way);
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rank_addr <<= shiftup;
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rank_addr |= ch_addr & GENMASK_ULL(shiftup - 1, 0);
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rank_addr -= RIR_OFFSET(pvt->info.type, reg);
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mtype = pvt->info.get_memory_type(pvt);
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rankid = *rank;
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if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
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sb_decode_ddr4(mci, base_ch, rankid, rank_addr, msg);
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else
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sb_decode_ddr3(mci, base_ch, rankid, rank_addr, msg);
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} else {
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msg[0] = '\0';
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}
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edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
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n_rir,
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ch_addr,
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@ -2950,7 +3079,7 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
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struct mem_ctl_info *new_mci;
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struct sbridge_pvt *pvt = mci->pvt_info;
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enum hw_event_mc_err_type tp_event;
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char *optype, msg[256];
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char *optype, msg[256], msg_full[512];
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bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
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bool overflow = GET_BITFIELD(m->status, 62, 62);
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bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
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@ -3089,18 +3218,17 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
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*/
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if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
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channel = first_channel;
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snprintf(msg, sizeof(msg),
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"%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
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snprintf(msg_full, sizeof(msg_full),
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"%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d %s",
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overflow ? " OVERFLOW" : "",
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(uncorrected_error && recoverable) ? " recoverable" : "",
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area_type,
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mscod, errcode,
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socket, ha,
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channel_mask,
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rank);
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rank, msg);
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edac_dbg(0, "%s\n", msg);
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edac_dbg(0, "%s\n", msg_full);
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/* FIXME: need support for channel mask */
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@ -3111,7 +3239,7 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
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edac_mc_handle_error(tp_event, mci, core_err_cnt,
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m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
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channel, dimm, -1,
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optype, msg);
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optype, msg_full);
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return;
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err_parsing:
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edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
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