From d3274f20df58f58bab86a6b28c90676f75feb525 Mon Sep 17 00:00:00 2001 From: Eli Billauer Date: Thu, 4 Sep 2014 17:47:54 +0300 Subject: [PATCH] staging: xillybus: Reorganize line breaks for clarity Suggested-by: Dan Carpenter Signed-off-by: Eli Billauer Reviewed-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/xillybus/xillybus_core.c | 29 +++++++++++------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/staging/xillybus/xillybus_core.c b/drivers/staging/xillybus/xillybus_core.c index 04c60c64fc89..53ec54264dc4 100644 --- a/drivers/staging/xillybus/xillybus_core.c +++ b/drivers/staging/xillybus/xillybus_core.c @@ -770,14 +770,11 @@ static ssize_t xillybus_read(struct file *filp, char __user *userbuf, bytes_done += howmany; if (bufferdone) { - channel->endpoint->ephw-> - hw_sync_sgl_for_device - ( - channel->endpoint, - channel->wr_buffers[bufidx]-> - dma_addr, - channel->wr_buf_size, - DMA_FROM_DEVICE); + channel->endpoint->ephw->hw_sync_sgl_for_device( + channel->endpoint, + channel->wr_buffers[bufidx]->dma_addr, + channel->wr_buf_size, + DMA_FROM_DEVICE); /* * Tell FPGA the buffer is done with. It's an @@ -1031,7 +1028,9 @@ static int xillybus_myflush(struct xilly_channel *channel, long timeout) bufidx = channel->rd_host_buf_idx; - bufidx_minus1 = (bufidx == 0) ? channel->num_rd_buffers - 1 : bufidx-1; + bufidx_minus1 = (bufidx == 0) ? + channel->num_rd_buffers - 1 : + bufidx - 1; end_offset_plus1 = channel->rd_host_buf_pos >> channel->log2_element_size; @@ -1320,13 +1319,11 @@ static ssize_t xillybus_write(struct file *filp, const char __user *userbuf, bytes_done += howmany; if (bufferdone) { - channel->endpoint->ephw-> - hw_sync_sgl_for_device( - channel->endpoint, - channel->rd_buffers[bufidx]-> - dma_addr, - channel->rd_buf_size, - DMA_TO_DEVICE); + channel->endpoint->ephw->hw_sync_sgl_for_device( + channel->endpoint, + channel->rd_buffers[bufidx]->dma_addr, + channel->rd_buf_size, + DMA_TO_DEVICE); mutex_lock(&channel->endpoint->register_mutex);