drm/amd/pm: unify the interface for power gating
No need to have special handling for swSMU supported ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -927,7 +927,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
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{
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int ret = 0;
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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bool swsmu = is_support_sw_smu(adev);
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switch (block_type) {
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case AMD_IP_BLOCK_TYPE_UVD:
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@ -968,15 +967,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
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case AMD_IP_BLOCK_TYPE_GFX:
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case AMD_IP_BLOCK_TYPE_VCN:
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case AMD_IP_BLOCK_TYPE_SDMA:
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if (pp_funcs && pp_funcs->set_powergating_by_smu) {
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ret = (pp_funcs->set_powergating_by_smu(
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(adev)->powerplay.pp_handle, block_type, gate));
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}
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break;
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case AMD_IP_BLOCK_TYPE_JPEG:
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if (swsmu)
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ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
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break;
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case AMD_IP_BLOCK_TYPE_GMC:
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case AMD_IP_BLOCK_TYPE_ACP:
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if (pp_funcs && pp_funcs->set_powergating_by_smu) {
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@ -1270,9 +1270,6 @@ bool is_support_sw_smu(struct amdgpu_device *adev);
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bool is_support_cclk_dpm(struct amdgpu_device *adev);
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int smu_write_watermarks_table(struct smu_context *smu);
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/* smu to display interface */
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extern int smu_dpm_set_power_gate(void *handle, uint32_t block_type, bool gate);
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int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t *min, uint32_t *max);
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@ -268,9 +268,9 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
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* Under this case, the smu->mutex lock protection is already enforced on
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* the parent API smu_force_performance_level of the call path.
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*/
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int smu_dpm_set_power_gate(void *handle,
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uint32_t block_type,
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bool gate)
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static int smu_dpm_set_power_gate(void *handle,
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uint32_t block_type,
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bool gate)
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{
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struct smu_context *smu = handle;
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int ret = 0;
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