powerpc/64s/exception: remove EXCEPTION_PROLOG_0/1, rename _2
EXCEPTION_PROLOG_0 and _1 have only a single caller, so expand them into it. Rename EXCEPTION_PROLOG_2_REAL to INT_SAVE_SRR_AND_JUMP and EXCEPTION_PROLOG_2_VIRT to INT_VIRT_SAVE_SRR_AND_JUMP, which are more descriptive. No generated code change except BUG line number constants. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190802105709.27696-24-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin
Michael Ellerman
parent
9b40f62b8a
commit
d29768e13c
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@ -180,77 +180,7 @@ BEGIN_FTR_SECTION_NESTED(943) \
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std ra,offset(r13); \
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END_FTR_SECTION_NESTED(ftr,ftr,943)
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.macro EXCEPTION_PROLOG_0 area
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SET_SCRATCH0(r13) /* save r13 */
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GET_PACA(r13)
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std r9,\area\()+EX_R9(r13) /* save r9 */
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OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
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HMT_MEDIUM
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std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
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OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
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.endm
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.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, dar, dsisr, bitmask
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OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
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OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
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INTERRUPT_TO_KERNEL
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SAVE_CTR(r10, \area\())
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mfcr r9
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.if \kvm
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KVMTEST \hsrr \vec
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.endif
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.if \bitmask
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lbz r10,PACAIRQSOFTMASK(r13)
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andi. r10,r10,\bitmask
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/* Associate vector numbers with bits in paca->irq_happened */
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.if \vec == 0x500 || \vec == 0xea0
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li r10,PACA_IRQ_EE
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.elseif \vec == 0x900
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li r10,PACA_IRQ_DEC
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.elseif \vec == 0xa00 || \vec == 0xe80
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li r10,PACA_IRQ_DBELL
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.elseif \vec == 0xe60
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li r10,PACA_IRQ_HMI
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.elseif \vec == 0xf00
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li r10,PACA_IRQ_PMI
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.else
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.abort "Bad maskable vector"
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.endif
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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bne masked_Hinterrupt
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FTR_SECTION_ELSE
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bne masked_interrupt
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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bne masked_Hinterrupt
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.else
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bne masked_interrupt
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.endif
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.endif
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std r11,\area\()+EX_R11(r13)
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std r12,\area\()+EX_R12(r13)
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/*
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* DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
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* because a d-side MCE will clobber those registers so is
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* not recoverable if they are live.
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*/
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GET_SCRATCH0(r10)
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std r10,\area\()+EX_R13(r13)
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.if \dar
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mfspr r10,SPRN_DAR
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std r10,\area\()+EX_DAR(r13)
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.endif
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.if \dsisr
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mfspr r10,SPRN_DSISR
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stw r10,\area\()+EX_DSISR(r13)
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.endif
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.endm
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.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
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.macro INT_SAVE_SRR_AND_JUMP label, hsrr, set_ri
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ld r10,PACAKMSR(r13) /* get MSR value for kernel */
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.if ! \set_ri
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xori r10,r10,MSR_RI /* Clear MSR_RI */
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@ -293,7 +223,8 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
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b . /* prevent speculative execution */
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.endm
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.macro EXCEPTION_PROLOG_2_VIRT label, hsrr
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/* INT_SAVE_SRR_AND_JUMP works for real or virt, this is faster but virt only */
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.macro INT_VIRT_SAVE_SRR_AND_JUMP label, hsrr
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#ifdef CONFIG_RELOCATABLE
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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@ -620,7 +551,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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* This is done if early=2.
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*/
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.macro INT_HANDLER name, vec, ool=0, early=0, virt=0, hsrr=0, area=PACA_EXGEN, ri=1, dar=0, dsisr=0, bitmask=0, kvm=0
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EXCEPTION_PROLOG_0 \area
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SET_SCRATCH0(r13) /* save r13 */
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GET_PACA(r13)
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std r9,\area\()+EX_R9(r13) /* save r9 */
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OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
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HMT_MEDIUM
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std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
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OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
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.if \ool
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.if !\virt
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b tramp_real_\name
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@ -632,16 +569,74 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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TRAMP_VIRT_BEGIN(tramp_virt_\name)
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.endif
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.endif
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EXCEPTION_PROLOG_1 \hsrr, \area, \kvm, \vec, \dar, \dsisr, \bitmask
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OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
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OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
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INTERRUPT_TO_KERNEL
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SAVE_CTR(r10, \area\())
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mfcr r9
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.if \kvm
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KVMTEST \hsrr \vec
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.endif
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.if \bitmask
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lbz r10,PACAIRQSOFTMASK(r13)
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andi. r10,r10,\bitmask
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/* Associate vector numbers with bits in paca->irq_happened */
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.if \vec == 0x500 || \vec == 0xea0
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li r10,PACA_IRQ_EE
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.elseif \vec == 0x900
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li r10,PACA_IRQ_DEC
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.elseif \vec == 0xa00 || \vec == 0xe80
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li r10,PACA_IRQ_DBELL
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.elseif \vec == 0xe60
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li r10,PACA_IRQ_HMI
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.elseif \vec == 0xf00
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li r10,PACA_IRQ_PMI
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.else
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.abort "Bad maskable vector"
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.endif
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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bne masked_Hinterrupt
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FTR_SECTION_ELSE
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bne masked_interrupt
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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bne masked_Hinterrupt
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.else
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bne masked_interrupt
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.endif
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.endif
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std r11,\area\()+EX_R11(r13)
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std r12,\area\()+EX_R12(r13)
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/*
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* DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
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* because a d-side MCE will clobber those registers so is
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* not recoverable if they are live.
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*/
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GET_SCRATCH0(r10)
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std r10,\area\()+EX_R13(r13)
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.if \dar
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mfspr r10,SPRN_DAR
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std r10,\area\()+EX_DAR(r13)
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.endif
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.if \dsisr
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mfspr r10,SPRN_DSISR
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stw r10,\area\()+EX_DSISR(r13)
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.endif
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.if \early == 2
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/* nothing more */
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.elseif \early
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mfctr r10 /* save ctr, even for !RELOCATABLE */
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BRANCH_TO_C000(r11, \name\()_early_common)
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.elseif !\virt
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EXCEPTION_PROLOG_2_REAL \name\()_common, \hsrr, \ri
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INT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr, \ri
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.else
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EXCEPTION_PROLOG_2_VIRT \name\()_common, \hsrr
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INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr
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.endif
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.if \ool
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.popsection
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@ -1852,7 +1847,7 @@ EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
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bne+ denorm_assist
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#endif
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KVMTEST EXC_HV 0x1500
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EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1
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INT_SAVE_SRR_AND_JUMP denorm_common, EXC_HV, 1
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EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
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#ifdef CONFIG_PPC_DENORMALISATION
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@ -1986,7 +1981,7 @@ EXC_VIRT_NONE(0x5800, 0x100)
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std r12,PACA_EXGEN+EX_R12(r13); \
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GET_SCRATCH0(r10); \
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std r10,PACA_EXGEN+EX_R13(r13); \
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EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1
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INT_SAVE_SRR_AND_JUMP soft_nmi_common, _H, 1
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/*
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* Branch to soft_nmi_interrupt using the emergency stack. The emergency
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