gpio: tc35894: Disable Direct KBD interrupts to enable gpio irq
On tc35894, have to disable direct keypad interrupts to make it as general purpose interrupts functionality work. if not, after chip reset, IRQST(0x91) will always 0x20, IRQN always low level, can't be clear. Configure DIRECTx to enable general purpose gpio mode, else read GPIOMISx register always zero in irq routine. verified on tc35894, need more test on other tc3589x. Signed-off-by: dillon min <dillon.minfei@gmail.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
parent
805a6ef8ac
commit
d284c16f84
|
@ -19,9 +19,9 @@
|
||||||
* These registers are modified under the irq bus lock and cached to avoid
|
* These registers are modified under the irq bus lock and cached to avoid
|
||||||
* unnecessary writes in bus_sync_unlock.
|
* unnecessary writes in bus_sync_unlock.
|
||||||
*/
|
*/
|
||||||
enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
|
enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };
|
||||||
|
|
||||||
#define CACHE_NR_REGS 4
|
#define CACHE_NR_REGS 5
|
||||||
#define CACHE_NR_BANKS 3
|
#define CACHE_NR_BANKS 3
|
||||||
|
|
||||||
struct tc3589x_gpio {
|
struct tc3589x_gpio {
|
||||||
|
@ -200,6 +200,7 @@ static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
|
||||||
[REG_IEV] = TC3589x_GPIOIEV0,
|
[REG_IEV] = TC3589x_GPIOIEV0,
|
||||||
[REG_IS] = TC3589x_GPIOIS0,
|
[REG_IS] = TC3589x_GPIOIS0,
|
||||||
[REG_IE] = TC3589x_GPIOIE0,
|
[REG_IE] = TC3589x_GPIOIE0,
|
||||||
|
[REG_DIRECT] = TC3589x_DIRECT0,
|
||||||
};
|
};
|
||||||
int i, j;
|
int i, j;
|
||||||
|
|
||||||
|
@ -228,6 +229,7 @@ static void tc3589x_gpio_irq_mask(struct irq_data *d)
|
||||||
int mask = BIT(offset % 8);
|
int mask = BIT(offset % 8);
|
||||||
|
|
||||||
tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
|
tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
|
||||||
|
tc3589x_gpio->regs[REG_DIRECT][regoffset] |= mask;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tc3589x_gpio_irq_unmask(struct irq_data *d)
|
static void tc3589x_gpio_irq_unmask(struct irq_data *d)
|
||||||
|
@ -239,6 +241,7 @@ static void tc3589x_gpio_irq_unmask(struct irq_data *d)
|
||||||
int mask = BIT(offset % 8);
|
int mask = BIT(offset % 8);
|
||||||
|
|
||||||
tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
|
tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
|
||||||
|
tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_chip tc3589x_gpio_irq_chip = {
|
static struct irq_chip tc3589x_gpio_irq_chip = {
|
||||||
|
@ -334,6 +337,17 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
|
/* For tc35894, have to disable Direct KBD interrupts,
|
||||||
|
* else IRQST will always be 0x20, IRQN low level, can't
|
||||||
|
* clear the irq status.
|
||||||
|
* TODO: need more test on other tc3589x chip.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
|
||||||
|
TC3589x_DKBDMSK_ELINT | TC3589x_DKBDMSK_EINT);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
ret = devm_request_threaded_irq(&pdev->dev,
|
ret = devm_request_threaded_irq(&pdev->dev,
|
||||||
irq, NULL, tc3589x_gpio_irq,
|
irq, NULL, tc3589x_gpio_irq,
|
||||||
IRQF_ONESHOT, "tc3589x-gpio",
|
IRQF_ONESHOT, "tc3589x-gpio",
|
||||||
|
|
|
@ -19,6 +19,9 @@ enum tx3589x_block {
|
||||||
#define TC3589x_RSTCTRL_KBDRST (1 << 1)
|
#define TC3589x_RSTCTRL_KBDRST (1 << 1)
|
||||||
#define TC3589x_RSTCTRL_GPIRST (1 << 0)
|
#define TC3589x_RSTCTRL_GPIRST (1 << 0)
|
||||||
|
|
||||||
|
#define TC3589x_DKBDMSK_ELINT (1 << 1)
|
||||||
|
#define TC3589x_DKBDMSK_EINT (1 << 0)
|
||||||
|
|
||||||
/* Keyboard Configuration Registers */
|
/* Keyboard Configuration Registers */
|
||||||
#define TC3589x_KBDSETTLE_REG 0x01
|
#define TC3589x_KBDSETTLE_REG 0x01
|
||||||
#define TC3589x_KBDBOUNCE 0x02
|
#define TC3589x_KBDBOUNCE 0x02
|
||||||
|
@ -101,6 +104,9 @@ enum tx3589x_block {
|
||||||
#define TC3589x_GPIOODM2 0xE4
|
#define TC3589x_GPIOODM2 0xE4
|
||||||
#define TC3589x_GPIOODE2 0xE5
|
#define TC3589x_GPIOODE2 0xE5
|
||||||
|
|
||||||
|
#define TC3589x_DIRECT0 0xEC
|
||||||
|
#define TC3589x_DKBDMSK 0xF3
|
||||||
|
|
||||||
#define TC3589x_INT_GPIIRQ 0
|
#define TC3589x_INT_GPIIRQ 0
|
||||||
#define TC3589x_INT_TI0IRQ 1
|
#define TC3589x_INT_TI0IRQ 1
|
||||||
#define TC3589x_INT_TI1IRQ 2
|
#define TC3589x_INT_TI1IRQ 2
|
||||||
|
|
Loading…
Reference in New Issue