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drm/gma500: Make all chips use gma_wait_for_vblank 

Also remove the duplicated oaktrail function.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
Patrik Jakobsson 2013-07-10 01:20:19 +02:00
parent ad3c46eae3
commit d1fa08f3ba
7 changed files with 17 additions and 29 deletions
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3
drivers/gpu/drm/gma500/cdv_intel_dp.c
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@ -34,6 +34,7 @@
#include "psb_drv.h" #include "psb_drv.h"
#include "psb_intel_drv.h" #include "psb_intel_drv.h"
#include "psb_intel_reg.h" #include "psb_intel_reg.h"
#include "gma_display.h"
#include <drm/drm_dp_helper.h> #include <drm/drm_dp_helper.h>
#define _wait_for(COND, MS, W) ({ \ #define _wait_for(COND, MS, W) ({ \
@ -1317,7 +1318,7 @@ cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
/* Enable output, wait for it to become active */ /* Enable output, wait for it to become active */
REG_WRITE(intel_dp->output_reg, reg); REG_WRITE(intel_dp->output_reg, reg);
REG_READ(intel_dp->output_reg); REG_READ(intel_dp->output_reg);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
DRM_DEBUG_KMS("Link config\n"); DRM_DEBUG_KMS("Link config\n");
/* Write the link configuration data */ /* Write the link configuration data */

6
drivers/gpu/drm/gma500/mdfld_intel_display.c
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@ -65,7 +65,7 @@ void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
} }
/* FIXME JLIU7_PO */ /* FIXME JLIU7_PO */
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
return; return;
/* Wait for for the pipe disable to take effect. */ /* Wait for for the pipe disable to take effect. */
@ -93,7 +93,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)
} }
/* FIXME JLIU7_PO */ /* FIXME JLIU7_PO */
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
return; return;
/* Wait for for the pipe enable to take effect. */ /* Wait for for the pipe enable to take effect. */
@ -1034,7 +1034,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
/* Wait for for the pipe enable to take effect. */ /* Wait for for the pipe enable to take effect. */
REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
mrst_crtc_mode_set_exit: mrst_crtc_mode_set_exit:

6
drivers/gpu/drm/gma500/oaktrail_crtc.c
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@ -242,7 +242,7 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
REG_READ(map->conf); REG_READ(map->conf);
} }
/* Wait for for the pipe disable to take effect. */ /* Wait for for the pipe disable to take effect. */
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
temp = REG_READ(map->dpll); temp = REG_READ(map->dpll);
if ((temp & DPLL_VCO_ENABLE) != 0) { if ((temp & DPLL_VCO_ENABLE) != 0) {
@ -484,10 +484,10 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
REG_WRITE(map->conf, pipeconf); REG_WRITE(map->conf, pipeconf);
REG_READ(map->conf); REG_READ(map->conf);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
REG_WRITE(map->cntr, dspcntr); REG_WRITE(map->cntr, dspcntr);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
oaktrail_crtc_mode_set_exit: oaktrail_crtc_mode_set_exit:
gma_power_end(dev); gma_power_end(dev);

12
drivers/gpu/drm/gma500/oaktrail_hdmi.c
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@ -155,12 +155,6 @@ static void oaktrail_hdmi_audio_disable(struct drm_device *dev)
HDMI_READ(HDMI_HCR); HDMI_READ(HDMI_HCR);
} }
static void wait_for_vblank(struct drm_device *dev)
{
/* Wait for 20ms, i.e. one cycle at 50hz. */
mdelay(20);
}
static unsigned int htotal_calculate(struct drm_display_mode *mode) static unsigned int htotal_calculate(struct drm_display_mode *mode)
{ {
u32 htotal, new_crtc_htotal; u32 htotal, new_crtc_htotal;
@ -372,10 +366,10 @@ int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc,
REG_WRITE(PCH_PIPEBCONF, pipeconf); REG_WRITE(PCH_PIPEBCONF, pipeconf);
REG_READ(PCH_PIPEBCONF); REG_READ(PCH_PIPEBCONF);
wait_for_vblank(dev); gma_wait_for_vblank(dev);
REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(dspcntr_reg, dspcntr);
wait_for_vblank(dev); gma_wait_for_vblank(dev);
gma_power_end(dev); gma_power_end(dev);
@ -459,7 +453,7 @@ void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode)
REG_READ(PCH_PIPEBCONF); REG_READ(PCH_PIPEBCONF);
} }
wait_for_vblank(dev); gma_wait_for_vblank(dev);
/* Enable plane */ /* Enable plane */
temp = REG_READ(DSPBCNTR); temp = REG_READ(DSPBCNTR);

16
drivers/gpu/drm/gma500/psb_intel_display.c
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@ -82,12 +82,6 @@ static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
clock->dot = clock->vco / clock->p; clock->dot = clock->vco / clock->p;
} }
void psb_intel_wait_for_vblank(struct drm_device *dev)
{
/* Wait for 20ms, i.e. one cycle at 50hz. */
mdelay(20);
}
static int psb_intel_pipe_set_base(struct drm_crtc *crtc, static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
int x, int y, struct drm_framebuffer *old_fb) int x, int y, struct drm_framebuffer *old_fb)
{ {
@ -244,7 +238,7 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
} }
/* Wait for vblank for the disable to take effect. */ /* Wait for vblank for the disable to take effect. */
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
temp = REG_READ(map->dpll); temp = REG_READ(map->dpll);
if ((temp & DPLL_VCO_ENABLE) != 0) { if ((temp & DPLL_VCO_ENABLE) != 0) {
@ -516,14 +510,14 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
REG_WRITE(map->conf, pipeconf); REG_WRITE(map->conf, pipeconf);
REG_READ(map->conf); REG_READ(map->conf);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
REG_WRITE(map->cntr, dspcntr); REG_WRITE(map->cntr, dspcntr);
/* Flush the plane changes */ /* Flush the plane changes */
crtc_funcs->mode_set_base(crtc, x, y, old_fb); crtc_funcs->mode_set_base(crtc, x, y, old_fb);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
return 0; return 0;
} }
@ -669,12 +663,12 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc)
REG_WRITE(map->base, crtc_state->saveDSPBASE); REG_WRITE(map->base, crtc_state->saveDSPBASE);
REG_WRITE(map->conf, crtc_state->savePIPECONF); REG_WRITE(map->conf, crtc_state->savePIPECONF);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
REG_WRITE(map->base, crtc_state->saveDSPBASE); REG_WRITE(map->base, crtc_state->saveDSPBASE);
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
paletteReg = map->palette; paletteReg = map->palette;
for (i = 0; i < 256; ++i) for (i = 0; i < 256; ++i)

1
drivers/gpu/drm/gma500/psb_intel_drv.h
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@ -246,7 +246,6 @@ extern struct drm_encoder *psb_intel_best_encoder(struct drm_connector
extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
struct drm_crtc *crtc); struct drm_crtc *crtc);
extern void psb_intel_wait_for_vblank(struct drm_device *dev);
extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);
extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev,

2
drivers/gpu/drm/gma500/psb_intel_sdvo.c
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@ -1121,7 +1121,7 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
if ((temp & SDVO_ENABLE) == 0) if ((temp & SDVO_ENABLE) == 0)
psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE); psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
psb_intel_wait_for_vblank(dev); gma_wait_for_vblank(dev);
status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2); status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
/* Warn if the device reported failure to sync. /* Warn if the device reported failure to sync.