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mmc: JZ4740: Add support for JZ4775 

Add support for the variant on the JZ4775 SoC from Ingenic. Let's also
clarify that the drive clock selection and sample clock selection have been
supported since JZ4775, not X1000. So, support for these two functions has
been added for JZ4775 and JZ4780.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/1623329930-14387-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
周琰杰 (Zhou Yanjie) 2021-06-10 20:58:50 +08:00 committed by Ulf Hansson
parent 3160e02536
commit d1c777ee5c
1 changed files with 3 additions and 2 deletions
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5
drivers/mmc/host/jz4740_mmc.c
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@ -674,7 +674,7 @@ static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
cmdat |= JZ_MMC_CMDAT_WRITE;
if (host->use_dma) {
/*
* The 4780's MMC controller has integrated DMA ability
* The JZ4780's MMC controller has integrated DMA ability
* in addition to being able to use the external DMA
* controller. It moves DMA control bits to a separate
* register. The DMA_SEL bit chooses the external
@ -866,7 +866,7 @@ static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
writew(div, host->base + JZ_REG_MMC_CLKRT);
if (real_rate > 25000000) {
if (host->version >= JZ_MMC_X1000) {
if (host->version >= JZ_MMC_JZ4780) {
writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY |
JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY |
JZ_MMC_LPM_LOW_POWER_MODE_EN,
@ -959,6 +959,7 @@ static const struct of_device_id jz4740_mmc_of_match[] = {
{ .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 },
{ .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B },
{ .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 },
{ .compatible = "ingenic,jz4775-mmc", .data = (void *) JZ_MMC_JZ4780 },
{ .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 },
{ .compatible = "ingenic,x1000-mmc", .data = (void *) JZ_MMC_X1000 },
{},