drm/amd/pm: decouple the watermark table setting from socclk/uclk dpms
As they have no real dependence. And for Navi1x, the socclk/uclk dpms are enabled after DAL initialization. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1818,17 +1818,16 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
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if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
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if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
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return -EOPNOTSUPP;
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return -EOPNOTSUPP;
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if (smu->disable_watermark)
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return 0;
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mutex_lock(&smu->mutex);
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mutex_lock(&smu->mutex);
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if (!smu->disable_watermark &&
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ret = smu_set_watermarks_table(smu, clock_ranges);
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smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
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smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
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ret = smu_set_watermarks_table(smu, clock_ranges);
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if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
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if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
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smu->watermarks_bitmap |= WATERMARKS_EXIST;
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smu->watermarks_bitmap |= WATERMARKS_EXIST;
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smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
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smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
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}
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}
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}
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mutex_unlock(&smu->mutex);
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mutex_unlock(&smu->mutex);
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